考慮對稱與規律性之類比電路擺置

Analog Placement with Symmetry and Regularity Considerations

周邦彥(Pang-Yen Chou)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.02791

摘要

對稱條件（symmetry constraint）與規律結構（regular structure）是類比佈局設計師在擺置元件時的兩大考量。對稱條件即是將兩個匹配元件matched modules）擺置於一個對稱軸兩端的相對位置以消減負面的電子效應。有經驗的類比擺置設計師亦常將元件擺置成規律結構以提昇電路的可繞性（routability）及減少多餘的繞線轉彎（wire bend）和穿孔代價（via cost）。為了同時考慮對稱條件與規律性，本論文提出異質階層式二元樹（heterogeneous B*-tree）擺置表現形式以及其對應的變換方式與優略衡量標準。實驗結果顯示我們提出的方法能有效地產生具高度規律性的擺置結果並且符合給定的條件。舉例而言，相較於文獻中最新的類比擺置工具，我們的方法使運作效能提升至18 倍，減少28%的面積，以及降低68%的繞線線長。擺置結果在經由全域繞線器繞線所獲得的結果也比過去的方法減少60%溢出量（overflow），減低39%穿孔，並且縮短的86%的繞線線長。

關鍵字

實體設計 ； 類比電路擺置 ； 對稱條件 ； 規律結構 ； 階層式二元樹

並列摘要

Symmetry constraints and regular structures are two major considerations for expert analog layout designers. Symmetry constraints are specified by designers to place matched modules symmetrically with respect to some common axes to reduce unwanted electrical effects. Regular structures are commonly followed by experienced analog layout designers to enhance routability and suppress parasitics induced by extra bends of wires and via cost. In this thesis, we propose a heterogeneous B*-tree representation to consider symmetry and regularity simultaneously. Corresponding moves and a new regularity cost modeling for the representation are also presented. Experimental results show that our approach can efficiently generate regularly structured placement satisfying all symmetry constraints. For example, our placer achieves a 18X runtime speedup, 28% smaller area, and 68% shorter wire length than the previous work, based on placement results, and 60% fewer overflows, 39% fewer vias, and 86% shorter routed wirelength, based on global routing results.

並列關鍵字

physical design ； analog placement ； symmetry constraint ； regular structure ； hierarchical B*-tree

參考文獻

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