摘要
隨積體電路製程逐年進步，金氧半電晶體閘極長度的縮短，造成其所能承受耐壓越來越低。為順應操作電壓因此逐漸降低趨勢，本論文之研究乃致力於適用於WiMAX直接降頻接收機架構之低電壓類比基頻電路的設計與製作。所包含之晶片以操作電壓區分共有1.0伏特，1.8伏特與0.5伏特操作三種晶片。 1.0伏特操作之類比基頻電路，採標準製程中提供之低臨界電壓之元件製作，並使用主動電阻電容方式達成低通濾波功能。七階柴比雪夫通道選擇濾波器之原型採用多級低階串接方式來實現之。濾波器並整合入可調變增益放大器之功能，使其輸出訊號能適合於其下一級類比數位轉換器之動態範圍。我們並採用伺服迴路架構，以減低直流漂移電壓之問題。量測結果3-dB頻寬為5.3MHz，可調增益範圍由20dB到50dB。晶片面積為0.7×1.1 mm2，消耗功率為9.9 mW。 1.8伏特之晶片採可調變增益與頻寬之設計以因應符合通訊標準。數位逐步趨近類比數位轉換器配合電流形式數位類比轉換器之設計，可用以解決直流漂移電壓問題。同一晶片上並有自動頻率校正迴路，利用主僕式校準方式，使濾波器不因製程或溫度變異而造成頻寬漂移。配合此校正迴路，可量測得精確3-dB頻寬於5.0MHz，10.0MHz及20.0MHz。此晶片可提供20~60dB之增益，整體面積為 1.5 × 2.0 mm2 ，消耗功率為 27.8mW。 相較於1.0伏特之晶片版本，0.5伏特操作之電路中電晶體使用標準臨界電壓之元件製作，利用基極電壓偏壓技巧及採最少電晶體堆疊架構，可使放大器於相當於元件臨界電壓值之低電源下操作。濾波器部份採跳蛙結構以合成五階柴比雪夫低通濾波器。由單一0.5伏特供應其電源，所消耗功率為 6.8mW。量測3-dB頻寬為2.6 MHz 。此外，由一外部電阻可調其增益範圍由0dB到9.8dB。晶片面積為 1.0 × 1.3mm2 。
並列摘要
As continuous improvement in the integrated circuit process, the gate-oxide breakdown voltage is declining due to the shrinking gate length of MOS-transistors. To go with the trend of descending supply voltage, this thesis is focused on the implementation of low voltage operation analog baseband circuits for WiMAX direct-conversion receivers. The realized chips in this work can be generally divided into three categories according to their operation voltages, namely 1.0-V, 1.8-V and 0.5-V. The 1.0-V analog baseband circuit was implemented with low threshold voltage devices provided by standard process while adopting the active–RC topology to achieve low-pass filtering. The 7th order Chebyshev channel selection filter prototype is realized through the cascade method. With a merged function of variable-gain amplifier, the output signal can accommodate to the dynamic range of the following ADC. The servo loop configuration is adopted to accomplish dc-offset cancellation. The circuit exhibited a 3-dB bandwidth of 5.3 MHz, a voltage gain from 20 to 50 dB while drawing 9.9 mW from a 1.0-V voltage supply. The die area is 0.7×1.1 mm2. The 1.8-V filter can switch to different gain levels and bandwidths to adapt to the communication standards. A successive approximation register ADC along with DAC current source array were used to achieve dc-offset cancellation. An automatic frequency tuning loop based on master-slave topology is implemented on the same chip to prevent the inaccuracy of filter bandwidth due to process and temperature variations. With this tuning loop, the precise filter bandwidth at 5.0 MHz, 10.0 MHz and 20.0 MHz can be obtained. The chip provides 20 to 60 dB gain and consumes 27.8 mW with a chip size of 1.5 × 2.0 mm2. In contrast with the 1.0-V version, a 0.5-V filter is implemented using standard devices with normal threshold voltage. Utilizing the body-biasing technique and adopting a structure with the fewest stacks of transistors enable the op-amp to operate under ultra low voltage comparable with device threshold voltage. The leapfrog structure is adopted to synthesize the 5th order Chebyshev low pass filter. While drawing 6.8 mW from a 0.5-V voltage supply, the filter demonstrated a 3-dB bandwidth of 2.6 MHz. In addition, the voltage gain can be varied from 0 to 9.8 dB through an external resistor. The die area is 1.0×1.3 mm2.