快速高斯雜訊產生器之設計與實作

Design and Implementation of a Fast Gaussian Noise Generator

王仁傑(Jen-Chieh Wang)

指導教授 ： 顧孟愷

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.02220

摘要

無資料

關鍵字

高斯雜訊 ； 實作 ； 硬體

並列摘要

In modern communication systems, powerful error control codes such as Turbo code and Low-Density Parity Check (LDPC) codes are employed to provide capacity approaching coding gains. Both of these codes have very low bit error rate. In order to properly verify these powerful error control codes, very long simulations in the order of billion samples are often necessary. Software-based simulation using Additive White Gaussian Noise (AWGN) is time consuming, and FPGA based simulations using hardware Gaussian noise generator reduce simulation time significantly. The throughput-area ratio is crucial to an AWGN generator because we can easily increase throughput by running multiple instances in parallel, and hence the chip size is the key point. Our design goal is to reduce chip size, increase throughput, and maintain noise quality at the same level of software programs. This thesis proposed architecture of a fast Gaussian noise generator base on Wallace method and this architecture has high throughput-area ratio. The noise quality of our design is very close to software programs. Implementation result of this design is at clock rate 183MHz and output two noise samples each clock ticks. And the throughput exceeds 18 billion by duplicating 100 instances. This high throughput would be capable of a verification part of next generation communication circuits.

並列關鍵字

Gaussian noise ； implementation ； hardware ； channel ； communication

參考文獻

[1] G.E.P. Box and M.E. Muller “A note on the generation of random normal deviates”, Ann. Math. Statist., vol. 29, pp. 610–611, 1958.

[2] C. Wallace, “Fast pseudorandom generators for normal and exponential variates”, ACM Trans. Math. Software, vol. 22, no. 1, pp. 119–127, 1996.

[3] W. Hörmann and J. Leydold, “Continuous random variate generation by fast numerical inversion,” ACM Transactions on Modeling and Computer Simulation, vol. 13, no. 4, pp. 347–362, 2003.

[4] D. Lee, W. Luk, J. Villasenor, P. Cheung, and Philip H. W. Leong, “A Hardware Gaussian Noise Generator Using the Wallace Method”, IEEE trans. VLSI Systems, Vol. 13, No. 8, August 2005.

[5] P. L’Ecuyer, “Maximally equidistributed combined Tausworthe generators,” Math. Comput., vol. 65, no. 213, pp. 203–213, 1996.