- 學位論文
離子佈植技術於量子穿隧元件的應用
Ion Implant Isolation for Quantum Tunneling Devices
摘要
對於傳統的金氧半場效電晶體(metal-oxide-semiconductor field-effect transistors, MOSFETs)而言，次臨界擺幅受到熱物理限制(> 60 mV/decade)，使得電晶體在關閉時的功率損耗並不會隨元件微縮而減少，反而會大幅地增加；而穿隧電晶體(tunnel field-effect transistor, TFET)可藉由閘極控制載子在源極與通道間的能帶穿隧機率的變化，使次臨界擺幅不再受到傳統的熱物理限制，而有效地降低電晶體的操作偏壓，進而減低漏電功耗。 為了研究穿隧機率，我們使用穿隧二極體結構來減少在電晶體因閘極而增加的複雜度，若要得到精確的穿隧電流密度，二極體的結構必須微縮至次微米或甚至是奈米等級，傳統的脊狀結構無法適用於探針量測，故我們提出利用離子佈植隔離技術來製作全平面化的二極體，並與傳統的脊狀結構與利用其他平面化製作(如BCB)的元件比較。由於離子佈植僅被廣泛運用於三五族半導體中，對於矽、鍺等四族半導體並沒有深入的研究，我們研究了在矽或鍺基板中，離子佈植隔離提供的高電阻率在不同佈植條件與退火溫度的影響，發現對於矽及鍺而言，其熱穩定度可達550℃和350℃。 本論文提出一個新穎的垂直穿隧電晶體元件結構及所需之製程步驟，藉由調整穿隧電場方向與閘極電場方向相同，並且利用隔離層來阻擋漏電以增近元件效能。我們利用TCAD軟體模擬此垂直穿隧電晶體，並研究結構中不同參數對於元件效能的影響，開關電流比最高可達107(Voverdrive =0.8 V)，最小的次臨界擺幅可低至6 mV/decade，次臨界擺幅小於60 mV/decade的電流範圍亦可達5個數量級。最後，我們製作矽鍺磊垂直穿隧電晶體，實驗數據顯示出開關電流比約為102，初步分析指向經蝕刻後的側壁品質對於閘極氧化層電容的影響甚大，藉由改善側壁氧化層品質以及元件結構，將可大幅改善穿隧電晶體的效能。
並列摘要
For conventional metal-oxide-semiconductor field-effect transistors, thermionic injection sets a limit to the subthreshold swing (> 60 mV/decade), leading to an increase of power consumption at off-state with the device scaling. Based on the modulation of the band-to-band tunneling probability by gate, a tunnel field-effect transistor (TFET) could overcome the thermionic limit and thus, provide a lower supply voltage and achieve lower power consumption. To investigate the tunneling probability, tunnel diodes are used because of its reduced complexity compared to TFETs. To estimate the tunnel current density, the diode size needs to be scaled down to sub-micrometer or even a smaller dimension. The mesa structure is not suitable for electrical probing, so we propose a full planarization process for the fabrication of tunnel diodes by ion implant isolation technology to compare with normal mesa structure and other planarized devices by BCB. The ion implant isolation process has been widely used in III-V semiconductor, but not yet for group IV semiconductors. To investigate the resistivity in silicon or germanium by ion implant, we investigate the effects of implant parameters and annealing temperature on the resistivity. The experiment results show that the thermal (budget) stability for silicon and germanium can be up to 550℃ and 350℃, respectively. We proposed a novel vertical TFET structure and its required process steps. By aligning the tunneling direction with the gate electric field and the insertion of the spacer layer between the source and the drain regions, the leakage current can be effectively suppressed. TCAD simulation was performed to study the effects of various structural parameters on vertical TFETs. The best Ion/Ioff is 107 (at Voverdrive =0.8 V), the minimal subthreshold swing (SSmin) is 6 mV/decade, and SS of less than 60 mV/decade was also obtained within five orders of magnitude of current. Last, we fabricated the SiGe TFET devices. The experimental data shows a poor Ion/Ioff of ~ 102. The preliminary analysis suggests the quality of the etched sidewall would affect the oxide capacitance, leading to poor electrostatic gate control. By improving the oxide/sidewall interfacial quality and optimizing the device structure, we expect to achieve a vertical TFET with much better performance.
參考文獻
延伸閱讀
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