考慮多重輸入變換與最大電路延遲之測試訊號產生技術

Test Pattern Generation for Maximum Circuit Delay under Simultaneous Input Transition Model

李晨豪(Chen-Hao Lee)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.02372

摘要

本篇論文提出一種新的時序分析方法，不同於傳統中只考慮單邊轉換的靜態時序分析，它可能提供使用者比靜態時序分析更大的電路延遲。此演算法主要的部分有：(1) 使用靜態時序分析取得電路初使的關鍵路徑。 (2) 我們利用正規引擎去對這條關鍵路徑作謬誤路徑的確認。 (3) 如果這條關鍵路徑是存在的，我們會試著在考慮電路多重輸入轉換的情況下找出相關的最大延遲測試訊號。 (4) 如果我們能找出前述的測試訊號，我們會用動態時序分析來驗證我們得到的最大電路延遲。如此一來我們的時序分析方法可以提供使用者作電路關鍵路徑的確認，並且能在不錯的效率下找出最大的電路延遲測試訊號，這些測試訊號對使用者在電路佈局的時序模擬是相當有幫助的。

關鍵字

靜態時序分析 ； 動態時序分析 ； 多重變換 ； 測試訊號 ； 布林限制 ； 可滿足性問題

並列摘要

In this thesis, we propose a new timing analysis method which is different from traditional ones. Our method consists of several steps：(1) We use static timing analysis (STA) to find out an initial critical path in the circuit. (2) We perform false path checking on the critical path by the Boolean Satisfiability (SAT) engine. (3) If the critical path is a true path (i.e. not false), we will try to push the delay bound obtained in the STA process by considering simultaneous input transitions of the circuit. (4) If we get certain input patterns from SAT engine, then we can evaluate the new delay data by dynamic timing analysis (DTA). In this way we can get an accurate delay bound and solve the circuit false path problem at the same time. Moreover, because we only simulate several input patterns in the circuit, the performance of our method must be better than traditional DTA. In our experiments, we demonstrate that our method can achieve both better performance and accuracy than random simulation. Finally we believe that the test patterns we derive by the SAT engine would be useful and important to the post-layout timing simulation stage.

並列關鍵字

STA ； DTA ； multiple transitions ； test patterns ； Boolean constraints ； SAT

參考文獻

[2] 陳麒旭, “靜態時序分析（Static Timing Analysis）基礎及應用”, http://www.chip123.com/article/Static Timing Analysis01.htm

[4] Eun Sei Park, M. Ray Mercer, "An Efficient Delay Test Generation System for Combinational Logic Circuits", Annual ACM IEEE Design Automation Conference

[12] 黃俊輔, “Quick RTL Synthesis for Design Analysis and Verification”, 國立台灣大學電機工程學研究所碩士論文.

Reference

[1] J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan, “Interconnect Design for Deep Submicron ICs”, Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 478-485, November 1997.