針對影像處理智財之覆蓋率導向驗證平台架構

Coverage directed testbench generation for still image CODEC IP's

羅偉倫(Wei-Lung Lo)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.02163

摘要

在IC設計流程?媗褌狺w成為主要的瓶頸,其中一個困難點是要如何確定RTL程式碼正確性,針對靜態畫面壓縮的矽智財,本文提出一個可以得到極高驗證覆蓋率的試圖騰架構.
在此架構內,模板以相同大小的方塊組成,方塊內有高,低頻的成分.
這些高低頻成分的比例和位置都以模擬退火演算法決定.
此方法用在四個影像處理編解碼矽智財上,並把用此方法得到的驗證覆蓋率,和其他設計者提供,
或傳統圖騰得到的驗證覆蓋率作比較,結果都是本文提出的方法能得到最好的效果

關鍵字

驗證 ； 矽智財 ； 影像處理

並列摘要

Verification has become the bottleneck in the hardware design process, and
one of the hardest verification problems is to verify the correctness of the RTL code.
In this paper, a testbench configuration to obtain high toggle coverage for still
CODEC image IP's is proposed.
In the configuration, an image template composed of key image characteristics, e.g., high
and low spatial frequency components, is proposed as the basic building block of the
testbench.
The parameters of each building block, including the ratio and location of the high/low frequency
components, are determined by simulated annealing.
The proposed testbench is applied to four image CODEC IPs.
Compared to the designer-provided image, commonly used verification images and random images,
the testbench generated by proposed method can achieve the highest toggle coverage.

並列關鍵字

verification ； testbench ； generation ； still-image ； IP

參考文獻

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