應用於正交分頻多工系統之決策反饋束波成型及通道等化之聯合演算法及FPGA雛型驗證

Joint Decision-Directed Beamforming and Channel Equalization Algorithm for OFDM Systems and Its FPGA Evaluation

陳俊宏(Chun-Hung Chen)

指導教授 ： 汪重光

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10893

摘要

隨著無線通訊應用之發展，對於無線區域網路的容量需求也隨之上升。在先進之無線區域網路規格中，為了提供更高的資料傳輸速率，通常會採用較寬的訊號頻寬。然而，由於可使用的ISM頻段是有限的，訊號頻寬或是網路使用者之增加，會造成同通道干擾的問題，並使得無線區域網路的吞吐量下降。因此，為了消除同通道干擾，本論文將研究應用於正交分頻多工系統中之束波成型技術。
針對正交分頻多工系統在追蹤階段之同通道干擾及通道等化誤差，本論文提出一決策反饋束波成型及通道等化之聯合演算法。此演算法是根據最小均方誤差的準則，定義出其單一成本函數。束波成型器權重及通道等化器係數之最佳估計值，可透過最小均方誤差演算法遞迴求得。為了增加束波成型器權重估計之準確性，估測誤差是由通道等化器輸出端的所有子載波取得。系統模擬的結果顯示，此聯合演算法可有效地降低殘餘之同通道干擾及通道等化誤差。
此外，考量到聯合演算法之硬體複雜度，本論文亦提出一低運算週期及高能量效益之遞迴式離散傅立葉(反)轉換之演算法。透過輸入分取之技巧，可減少75%的遞迴週期。由於遞迴週期之減少，此演算法可降低58.7%的實數乘法運算及78.9%的實數加法運算。為了更加簡化硬體的複雜度，此遞迴式離散傅立葉(反)轉換處理器中所需之常數乘法器可由位移器及加法器來實現，並透過有號位數表示式之最佳化以得到最小的加法器數目。
最後，所提出之遞迴式離散傅立葉(反)轉換之處理器，透過FPGA進行雛型驗證。後端實體設計的部分使用0.18微米CMOS製程技術，其核心面積為0.37×0.37毫米平方。根據佈局後之模擬結果，本設計在40 MHz工作頻率及1.8 伏特供應電壓下，消耗5.16 毫瓦。

關鍵字

束波成型 ； 通道等化 ； 聯合演算法 ； 正交分頻多工系統 ； 遞迴式離散傅立葉(反)轉換

並列摘要

The demand for high-throughput wireless local area network (WLAN) has greatly increased in recent years. Normally, large channel bandwidth is adopted in advanced WLAN standards to provide high data rate transmissions. However, since the available ISM band is limited, the extension of channel bandwidth may cause the co-channel interferences (CCIs), which can significantly degrade the throughput of a WLAN. In order to eliminate the CCIs, the beamforming technology can be used in the orthogonal frequency-division multiplexing (OFDM) systems.
In this thesis, a joint decision-directed beamforming and channel equalization algorithm is presented for OFDM systems in the presence of CCI. The cost function of the joint algorithm is proposed to minimize the mean-square decision error. The optimal estimations of beamformer weights and channel equalization coefficients are iteratively obtained with the gradient-based LMS algorithm. In order to increase the accuracy of weight estimation, the estimation errors for adaptation are extracted from the equalizer output on both pilot and data subcarriers. Simulation results show that the joint algorithm can provide 2.2 dB and 3 dB SNR gains at BER of 10^(−5) for QPSK and 16-QAM modulations, respectively, as compared with the conventional pilot-aided beamforming algorithm.
In order to reduce the hardware complexity of this algorithm, a low-computation-cycle and energy-efficient recursive DFT/IDFT (RDFT/RIDFT) algorithm is also presented. The proposed RDFT/RIDFT architecture consists of a pre-processor, a decimation buffer, and a recursive filter. The pre-processor performs the input-decimation technique to combine the input sequence into smaller groups, which can save 75% of recursion cycles of the recursive filter. Due to the reduction in recursion cycles, 58.7% of real multiplications and 79.8% of real additions can be decreased. Besides, the constant multiplier with shift-and-add approach is employed to replace the complex multiplication operation. The optimized signed-digit representation of twiddle factors is derived to minimize the number of adders in the multiplier, and thus lower the area and power consumption. Finally, the functionalities of the RDFT/RIDFT algorithm are verified by FPGA emulation. The physical implementation result shows that the core area of this design is 0.37×0.37 mm^2 with 0.18 μm CMOS process. The power consumption is 5.16 mW with 1.8 V supply voltage and 40 MHz clock rate.

並列關鍵字

beamforming ； channel equalization ； joint algorithm ； OFDM ； recursive DFT/IDFT

參考文獻

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