覆晶轉接特性量測與多層結構中改善性能之電感及較高製程變異容忍度之耦合電感設計

這篇論文包含了三個研究主題，第一個研究主題為毫米波頻帶之覆晶轉接特性之量測，第二個為低溫共燒陶瓷中效能改善之電感，最後是在多層結構中較高製程變異容忍度的電容與耦合電感之設計。由資料研讀及模擬結果可知傳統覆晶的轉接特性，並且關於其的窄、寬頻的改善方法也一並討論及模擬。然後我們使用兩種量測方法來量測覆晶的特性，一種是背對背的覆晶量測方法，另一種則是埠數降低量測法。在此，設計並且模擬一個使用於埠數降低量測法中的互補場效電晶體可程式負載之電路。為了設計一個高效能電感，我們探討且分析了電感內的物理現象及電感幾何結構對於電感效能的影響。然後我們設計了單層螺旋型、多層螺旋型、螺旋狀及立體螺線管的電感，並且比較其電感值、品質因素及自振頻率。為了改善電感效能，我們設計了部分接地層掏空及圖樣接地層結構之電感。最後設計了應用於差動電路的中心外接之對稱電感，以增加其的電路對稱特性。全部的電感設計都是在低溫共燒陶瓷的製程中完成。由於現今多層結構中製程仍存在著相當的變異，使得層與層之間無法完全對齊而造成其中的電路特性偏移。為了解決此問題，我們提出了較高製程變異容忍度的電容及耦合電感之設計。經由較高製程變異容忍度的元件設計出傳輸零點電路及帶通濾波器以驗證其對電路系統的效能改善。

關鍵字

flip-chip ； LTCC ； PRM ； Inductors ； spiral ； multilayer ； helical ； solenoid ； patterned ground ； hollow ground ； center tapped ； process tolerance ； misalignment ； coupled inductor

並列摘要

There are three topics in this thesis. The first topic is the flip-chip transition measurement up to millimeter wave frequency. The second is the design of performance improved inductors in the LTCC substrate. The last is the capacitor and coupled inductor with high process tolerance in the multilayer structure. The characteristics of the conventional flip-chip are studied and obtained by the simulation. Its narrowband and wideband improvements are simulated and presented. Then we propose two measurement methods to extract the property of the flip-chip up to millimeter wave frequency. One is back-to-back flip-chip measurement method and the other is PRM (port reduction method). The programmable termination in CMOS circuit is designed and simulated for PRM. To optimize the inductor design, the influence of the geometry on the inductor’s performance are introduced and analyzed. Then the spiral, multilayer, helical and solenoid inductors are designed and its performance on inductance, quality factor and self resonant frequency are compared. The spiral inductors with patterned or hollow ground are analyzed and designed to improve its performance. Finally, the center tapped inductors are designed for differential circuit with better symmetry property. All of inductors are designed in the LTCC substrate. The capacitor and coupled inductor with high process tolerance are proposed to withstand the misalignment between stacked layers due to process variation. The transmission zero circuit and bandpass filter implemented with these components are designed and simulated to test the performance of high process tolerance in the circuit level.

並列關鍵字

覆晶；低溫共燒陶瓷；埠數降低量測法；電感；螺旋；多層；螺旋狀；立體螺旋；圖樣接地層；部分接地層掏空；中心外接；製程變異容忍度；偏移；耦合電感

參考文獻

Albert Sutono, Joy Laskar and W. R. Smith, “Design of miniature multilayer on-package integrated image-reject filters,” IEEE Trans. Microwave Theory and Tech., vol. 51, no. 2, pp. 156~162. Jan. 2003.

Lap Kun Yeung and Ke-Li Wu, “A Compact second-order LTCC bandpass filter with two finite transmission zeros,” IEEE Trans. Microwave Theory and Tech., vol. 51, no. 2, pp. 337~341, Feb. 2003.

Heinrich W.,“The flip-chip approach for millimeter wave packaging,” IEEE Microwave Magazine., Vol. 6, no. 3, pp. 36 - 45, Sep. 2005.

Stephen H. Hall, Garrett W. Hall, James A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Wiley, 2000.

M.R.Gongora-Rubio, P.Espinoza-Vallejos et al, "Overview of low temperature cofired ceramics tape technology for Meso-System Technology (MsST)," Sensors and Actuators, Vol. A 89, 2001, pp. 222-241.

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覆晶轉接特性量測與多層結構中改善性能之電感及較高製程變異容忍度之耦合電感設計

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