透過您的圖書館登入
IP:3.22.248.208
  • 學位論文

一個使用合併電壓與電流感測控制方法之切換式電容直流電壓轉換器

A Switched Capacitor DC-DC Converter Using Hybrid of Voltage and Current Sensing Control Method

指導教授 : 陳信樹

摘要


近年來,在低功耗穿戴式裝置晶片中,人們更加關注切換式電容直流電壓轉換器因其不需要電感元件故可大幅降低成本以及晶片面積,本作品為一個以互補式金屬氧化物半導體(CMOS)製作之的除二降壓切換式電容直流電壓轉換器,並包含完整的設計、下線以及量測,此篇論文提出根據負載電流大小能夠自動調整切換頻率,降低切換損耗(Switching loss)並提升負載電流範圍及整體效率,同時利用監測DCDC輸出電流以及負載電流來達成更快速的暫態反應速度,本直流轉換器對於輸入電壓從3.8V到5.4V都能提供1豪安培(mA)以上的抽載電流並維持輸出電壓1.8V。此晶片是以台積電 0.25μm 1P3M High Voltage Mixed Signal CMOS 製程製作。依據實驗結果,本晶片在瞬間抽載時,暫態反應時間約為200ns,負載電流範圍從20微安培(μA)到2.5豪安培(mA),最高效率為72.3%。

並列摘要


Recently, people pay high attention to switched capacitor (SC) DC-DC converters which don’t need inductors that can save a lot of cost and die area in the wearable devices. This work encompasses the complete design, fabrication, and measurement of a CMOS based 2:1 step-down switched capacitor DC-DC converter. This thesis proposed a method which can scale the frequency according to the load current to reduce switching losses and increase load current range as well as power efficiency. It can also achieve higher transient response by monitoring the current of switched capacitor DC-DC converter and load current at the same time. The converter provides a fixed output voltage of 1.8V at 1mA from an input voltage ranging from 3.8V to 5.4V. This chip is designed to be implemented in a TSMC 0.25-μm 1P3M High Voltage Mixed Signal CMOS process. According to measurement results, transient recovery time is about 200ns in step response. Output load current range is from 20μA to 2.5mA. The peak power efficiency is 72.3%.

並列關鍵字

DC-DC converter current-sensing

參考文獻


Reference
[1] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor dc–dc converters,” IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 841-851, Mar. 2008.
[2] V. W. Ng and S. R. Sanders, “Switched capacitor dc–dc converter: superior where the buck converter has dominated,” Ph.D. dissertation, EECS Dept., UC Berkeley Univ., Berkeley, CA, USA, 2011.
[3] A. K. Mal and R. Todani, “Non overlapping clock (NOC) generator for low frequency switched capacitor circuits,” IEEE Technology Students' Symposium, Kharagpur, pp. 226-231, 2011.
[4] M. D. Seeman, “A design methodology for switched-capacitor dcdc converters,” EECS Dept., UC Berkeley Univ., Berkeley, CA, USA, 2009.

延伸閱讀