應用於900 MHz GSM之低相位雜訊CMOS本地振盪器

Low Phase Noise CMOS Local Oscillator for 900 MHz GSM Application

張志偉(Chih-Wei Chang)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.10534

摘要

全球行動通訊系統(GSM)是當前應用最為廣泛的行動電話網路系統。在900 MHz GSM射頻前端系統中，接收機的靈敏度是最首要的考量。而對於發射機的信號源，偏移此主頻率外20 MHz處的相位雜訊，必須低於-162 dBc/Hz，因為此處的相位雜訊，剛剛好會落在接收機的頻段內，影響接收機的效能。-162 dBc/Hz的相位雜訊規格不容易達到。而讓相位雜訊效能不良原因，諸如射頻積體電路中，太薄的金屬厚度造成不良的電感品質因素、太低的電壓限制了信號源振幅、元件中本身的雜訊等。所以近幾年來，一些改善相位雜訊效能的技術紛紛被提出來，但是大多需要特製的晶片外部鎊線電感，此方法雖然可以採用較高品質因素的電感，但是須要額外的製程和線路空間。
有鑑於此，我們首先會介紹一個130奈米CMOS全積體化的900 MHz GSM低相位雜訊信號源，不需要額外鎊線電感。而為了要達到此嚴格的遠處相位雜訊效能，在GSM四倍頻的壓控振盪器中，我們採用了一個共振技術來改善相位雜訊。為了繼續改善相位雜訊，VCO之後接了兩級的低雜訊的除二電路。此外，我們在除頻器中採用了電荷穿越的技術，能改更進一步地改善相位雜訊效能。在量測的結果中，得到的很好的相位雜訊結果，在中心頻率915 MHz偏移20 MHz處的相位雜訊，量得-170dBc/Hz的效能，比900 MHz GSM 發射機的原定規格好得多。此信號源操作在1.2伏，10毫安的靜態電流消耗。
接下來我們會介紹一個180奈米的 ”單相位轉雙相位輸出”之真單相時脈(TSPC)的除二電路，操作電壓為1.2伏。此電路是在兩個TSPC除頻器之間，加上了一個相位移的技術，能把原來同相位的輸出轉換成差動輸出。而輸出的差動信號是相當的對稱一致，且相位誤差很低。輸入信號的頻率範圍可以從600 MHz到3 GHz，在操作頻寬內，量得相位誤差可低於2度。

關鍵字

低相位雜訊 ； 振盪器 ； 除頻器

並列摘要

The global system for mobile communications (GSM) is the technology that underpins most of the world’s mobile phone networks. In 900 MHz GSM RF front-end, the sensitivity of receiver is the primary performance concern. The signal source out-band phase noise at 20-MHz offsets of transmitter (TX), which interferes with receiver bands, is limited below -162 dBc/Hz. It’s not easy to achieve because of the thin metal layers、poor-Q inductors、low supply voltage and noise issues of the RF CMOS process. In recent years, some phase noise enhancement techniques for GSM applications had been proposed, but they always need off chip high-Q inductors, which require additional process steps and consume space.
Therefore, firstly, a fully integrated low phase noise signal source for 900 MHz GSM transceivers in 0.13-μm CMOS process is presented in this thesis. In order to meet the stringent requirement of far-out phase noise, the resonant technique is applied to the voltage-controlled oscillator (VCO) design at four-time GSM frequency. The VCO is followed by two low noise frequency dividers to enhance the phase noise. In addition, the charge feed-through technique is proposed for the first time to lower the overall phase noise. The measured output signal achieves an excellent phase noise of -170 dBc/Hz at 20-MHz offset from the 915-MHz carrier, which is far better than the 900 MHz GSM TX specification. The signal source is operated at 1.2 V and the dc current is 10 mA.
Then, we introduce a true single-phase clocked (TSPC) single to differential divide-by-two circuit in 0.18-μm CMOS process with 1.2V supply voltage. A phase shifting technique is used between the TSPC dividers, transforms the output waveforms from in-phase to differential. The outputs can be perfectly symmetric and differential with low phase error. The input operation frequency range is from 600 MHz to 3 GHz. The measured output phase errors are less than 2° for entire frequency range.

並列關鍵字

low phase noise ； oscillator ； divider

參考文獻

[1] A. A. Abidi, “High frequency noise measurements on FET’s with small dimensions,” IEEE Trans. Electron. Devices, vol. 33, pp. 1801–1805, Nov. 1986.

[2] C. M. Hung and K. K. O, “A Packaged 1.1GHz CMOS VCO with Phase Noise of –126dBc/Hz at a 600kHz Offset,” IEEE J. Solid-State Circuits, vol. 35, pp. 100–103, Jan. 2000.

[3] S. T. Lee, S. J. Fang et al., “A quad-band GSM-GPRS transmitter with digital auto-calibration,” IEEE J. Solid-State Circuits, vol. 39, pp. 2200–2214, Dec. 2004.

[4] C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, “An ultra low phase noise GSM local oscillator in a 0.09-μm standard digital CMOS process with no high-Q inductors,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 483–486, Jun. 2004

[5] 3GPP Technical specification 05.05 v 8.20.0, European Telecommunications Standards Institute (ETSI).