可變碼長的極性解碼器硬體設計與實現

Implementation of a Multiple Code-Length Polar Code Decoder Architecture

薄榮鴻(Jung-Hong Po)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.02843

摘要

通道編碼的概念是利用增加多餘的訊息，讓訊息在傳輸時能夠達到更佳的正確性，以消除通道傳輸過程中的雜訊。許多專家學者都致力於研究此系統，期望可以建構出一套在傳輸速率小於通道容量的條件下，可以有效傳送訊息的編碼系統。極性編碼(Polar Codes) 運用了通道分解將不同的通道容量算出來，並且使用巴氏參數，來計算出固定增加點，再使用接續取消解碼(Successive Cancellation Decoding)的方式下，理論上可以達到上述的需求。
在接續消除解碼的架構上，需要連續的解碼資料，即需要將前面解碼後的結果，然後繼續解碼下面的資料，這是一個相當沒有效率的解碼方式。因此我本文提之解碼的處理器之目標為降低對於接續消除解碼前面資訊的需求，並且將極性編碼迭代時所擁有的累積效果延續，希望可以將同一套硬體架構可以處理多種碼長，並且藉由修正處理單元(Processing Element)以達到提高解碼效率的硬體架構。最近的文章有使用軟數值(Soft Value)來當作計算的數值，這在模擬表現上能夠優於原始的狀況但是並沒有對其硬體產生出相對應的架構，但如結合我們所提供的想法在此架構上，可以有效建立出一個可實踐此方法的硬體架構，這是本論文的另一個主要研究內容。
在本篇論文中，我們使用了接續消除解碼的解碼演算法，在硬體架構上把解碼的架構做排程與規劃上做了更動，藉由單一的解碼架構，做出多種碼長都可處理的排程規劃。此外我們也提出了一個可以有效將軟數值解碼的極性編碼解碼器架構。我們實踐了一個架構可以減少1/4的時脈數目，並且可以解碼不同的碼長256，512不同碼率0.5以及0.75的架構，我們這樣的架構充分運用極性編碼的可變動性，實踐出一個可以應用於不同狀況時的解碼方式。

關鍵字

通道分解 ； 對稱容量 ； 巴氏參數 ； 固定增加點

並列摘要

Channel coding is a technique which adds redundancy to the messages in order to increase the reliability of transmission. Many works have been devoting to construct a coding scheme that can transmit messages reliably at rates set below the channel capacity. Polar code is one such scheme that can achieve channel capacity theoretically under successive cancellation (SC) decoding.
SC decoder needs to process data serially. New data generation needs to process previous information. Therefore, we can find that this decoder is a very inefficient structure. In this work, we proposed a processing element (PE) to solve the SC decoding problem. And we want to use the SC decoder symmetric structure to implement a hardware which can process information with different code lengths. Besides, there is an algorithm which uses the soft values to generate the partial sum information, which has a better performance. We also proposed a hardware structure to implement this algorithm efficiently, by modifying our SC PE.
Our goal is to implement an SC polar code decoder to process multiple code-length data. We use a modified PE to increase the SC polar decoder throughput. Our proposed polar code SC decoder has a higher through-put channel code structure and a multi-code word structure. Moreover, we proposed a soft-output output polar decoding structure to improve the decoder performance. And this decoder can process data and save 1/4 clock cycles. The code lengths can be 512 and 256 bits and code rate can be 0.5 and 0.75.

並列關鍵字

Symmetric Capacity ； Bhattacharyya Parameters ； Frozen Bits

參考文獻

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