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  • 學位論文

寄生運算最小化的低功率暫存器配置方法

A Novel Methodology to Minimize Spurious Operations for Low Power Register Allocation

指導教授 : 顧孟愷
共同指導教授 : 賴飛羆(Fei Pei Lai)

摘要


當運算器的輸入值改變就會造成它的一次開關行為而消耗動態功率。如果這種開關行為發生在運算器的空閒狀態我們稱它為〝寄生運算〞,會消耗不必要的功率。由此可知,輸入變數的配置會決定這種寄生運算是否會在運算器上發生。過去的研究曾提出一個在高階合成使用的變數配置技術,這種技術提出抑制寄生運算且不會增加暫存器或多餘電路的方法。在這篇論文中,我們提出新的方法及有效率的演算法可以解決變數配置的問題且得到最佳化的結果。我們將變數配置的問題轉換一個適當定義的兼容圖中的最小成本完全圖覆蓋問題,然後利用最大成本流量演算法解題,而其中,成本方程式是用寄生運算的數量來定義,我們提供一個有系統的方法計算寄生運算的數量。實驗結果驗證了,這種方法在高階合成的變數配置階段,確實可以找到寄生運算最小化的配置方法,進而減少功率的消耗。

並列摘要


A functional unit consumes dynamic power when a switching activity occurs which means the input values in the registers have changed. We call the occurrence of a switching activity to be spurious when the functional unit is in “idle”. Thereby the assignment method of input variables determines whether or not spurious operations get executed by functional units. Previous researches have presented a variable assignment technique which, when used in high-level synthesis, suppresses spurious operations without adding latches or any other circuitry in front of functional units or registers. In this thesis, we propose the novel methodology and efficient algorithms to solve the variable assignment problem optimally. We apply a graph-theoretical solution of formulating the register assignment problem as a minimum cost clique covering of an appropriately defined compatibility graph and solve it with a max-cost flow algorithm, where the cost function is defined by using the number of spurious operations. Experimental results confirm the viability and usefulness of the approach in minimizing spurious operations during the register assignment phase of the behavioral synthesis process.

參考文獻


[1] K. Roy and S. C. Prasad, Low Power CMOS VLSI Circuit Design, New York: John Wiley, 2000.
[2] M. Pedram and J. Rabey, Power-aware Design Methodologies, Kluwer, 2002
[3] D.D. Gajski et al. High-Level Synthesis: Introduction to Chip and System Design, Kluwer, 1992
[4] D.D. Gajski and R. Kuhn, “Guest Editors’ Introduction: New VLSI Tools,” IEEE Computer, Vol.16, No.12, pp.11-14, Dec. 1983.
[5] Luca Benini, “Leading Edge Low Power Design,” in Proc. ASP-DAC, 2003, pp. 385-389

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