當信號線穿過多層連通住結構時,在分析信號完整度的問題上必須考慮到兩個效應,包含了連通柱不連續效應所造成的反射以及在平行板層間傳遞的徑向傳播模態於接地面上所造成接地雜訊。 本論文提供了一個能夠快速模擬連通柱穿層結構特性的時域分析方法,這個方法結合了二維時域有限差分法與連通柱的等效電路模型,其中連通柱的等效電路模型是利用全波分析模擬軟體HFSS萃取所得,而全波分析方法能夠考慮連通柱結構所有可能產生的高頻電磁效應,這是全波分析方法優於準靜態方法的地方。將本方法與三維時域有限差分法作比較,兩者於連通柱的不連續性效應上顯示了同樣的結果,並且本方法所需要的模擬時間也遠較三維時域有限差分方法為少。 另外,經由改變連通柱的尺寸,可以發現連通柱等效電路的值與幾何結構的大小有一定的關係,因此可以得到一個與各項幾何參數比值有關的連通柱等效電路值的設計圖表。
When the signal propagates through the multi-layer via environment, in the signal integrity issues, it will suffer from two composite effects, including reflection caused by via discontinuity and ground bounce excited by radial mode of parallel plate. A new method is proposed in the thesis to demonstrate these effects in the time domain, which combines the 2-D FDTD field solver with the equivalent circuit model of via. The equivalent circuit model of via is extracted by the full wave solver HFSS, taking into account all electromagnetic effects of via in the high frequency. A 2-D FDTD solver is established to efficiently get the time domain waveform results as signal propagating through via without resorting to the time-consuming 3-D FDTD simulation. The time domain results of the proposed method have been compared with those by 3-D FDTD method (ApsimFDTD). They both show the same effects due to via discontinuity, which validate our approach. Furthermore, extensive simulations and scaling analysis are employed to calculate the inductance and capacitance values in the equivalent circuit model of via. The charts for characterizing the equivalent circuit versus via geometry would be given, which is very useful for practical designer.