基於IEEE802.16e標準之快速收斂低密度奇偶校驗編碼硬體解碼器設計與實作

Design and Implementation of a Fast Convergence LDPC Decoder for IEEE802.16e Standard

劉奕廷(Yi-Ting Liu)

指導教授 ： 顧孟愷

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.03053

摘要

在這篇論文，我們提出了基於一種先進動態情報排程的快速收斂排程方法用在低密度奇偶校驗編碼之解碼器。另外，我們設計了是用於此方法的硬體架構適用於IEEE 802.16e，也是大家所知的全球互通微波存取。從電腦模擬結果顯示，提出的方法跟水平階層解碼演算法比約減少解碼次數46.92%在信號雜訊比為1分貝之下和最大解碼次數設為20。另外，我們方法的位元錯誤率也只有可忽略的退步。我們實作提出演算法於賽靈思公司的元件可編程邏輯閘陣列版上驗證其正確性。實作結果得知額外的硬體開銷跟記憶體使用很小。因為較低的解碼次數，整個系統的吞吐量也提高許多。跟原本動態情報排程設計比較，我們提出的演算法之複雜度是低得多，而可以在硬體上很容易實作。

關鍵字

低密度奇偶校驗編碼 ； 快速收斂 ； 解碼器 ； 全球互通微波存取 ； 動態情報排程 ； 錯誤更正碼

並列摘要

In this thesis, we propose the fast convergence scheduling method based on the novel technique named Informed Dynamic Scheduling for low-density parity-check code decoder. In addition, we design the hardware architecture to fit with the proposed method applied to IEEE 802.16e standard which is known as WiMAX. From the computer simulation result, the proposed method decreases the decoding iteration up to 46.92% compared with the horizontal layer decoding algorithm when Signal-to-noise ratio is 1dB and the maximum decoding iteration is 20. Furthermore, the BER performance of our method has only small degradation which can be ignored. We also implement the proposed algorithm on Xilinx FPGA board to verify the correctness. The implementation result shows that the extra hardware cost and memory usage is small. The total system throughput also improves because of the lower decoding iterations. Compare with the origin Informed Dynamic Scheduling method, the complexity of our proposed algorithm is much lower that can be implemented on the hardware easily.

並列關鍵字

LDPC ； Fast Convergence ； Decoder ； WiMAX ； Informed Dynamic Scheduling ； Channel Coding

參考文獻

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