節能微小之互補金氧半導體感測器介面電路設計

Design of Energy- and Area-Efficient CMOS Sensor Interface Circuits

凃智展(Chih-Chan Tu)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2018年)

https://doi.org/10.6342/NTU201800769

摘要

在傳統感測器介面電路中，放大器與類比數位轉換器往往分開設計，不僅耗費硬體面積且不具能量效益。本論文著重於設計能夠直接使用於感測器介面的類比數位轉換器，同時能滿足放大器需要的規格。本論文設計的三個類比數位轉換器皆為連續時間三角積分架構，連續時間的特性可避免離散時間設計出現的雜訊疊頻問題，而三角積分架構則可使節省硬體的量化器達到高信噪比。
　　本論文的第一個晶片實現於180奈米製程。我們從電容耦合放大器的架構出發，在回授電路前置入一位元量化器，直接改造成三角積分數位轉換器。由於一位元的回授訊號參雜過多的量化雜訊，造成迴路內積分器非線性，我們在回授網路之中使用了有限脈衝響應數位濾波器，與傳統使用類比濾波器相比可節省相當的面積。為維持頻寬穩定，積分器必須在晶片上設計為低頻寬，我們使用電流分流技術，可以大幅節省需要的電容，同時維持足夠的雜訊性能。此晶片使用1.8 V作為供應電壓，功率消耗為126 μW。在80 mVpp的輸入以及2 kHz的頻寬下，可以達到75.1 dB的信噪比，晶片面積為0.2 mm2。
　　在第二與第三個晶片中，為了能夠適應製程演進與物聯網低功耗的需求，我們使用40奈米製程，也將供應電壓降為1.2Ｖ。在低電壓操作的要求之下，我們利用壓控震盪器取代類比積分器，實現感測器前端電路。在第二個晶片中，我們設計一個能符合感測器介面要求的壓控震盪器，並加入截波技術降低閃爍雜訊，在17 μW的功率消耗下，能夠在8 mVpp以及5 kHz的頻寬下，解析出62 dB的信噪比，晶片面積只消耗0.0145 mm2。在第三個晶片中，我們在壓控震盪器外面使用第一顆晶片的電容回授架構，提升系統線性度，大幅提高訊號可輸入範圍至100 mVpp。在21 μW的功率消耗與2 kHz的頻寬下，可以達到74.9 dB的信噪比，並擁有-82 dB的總諧波失真，晶片面積為0.06 mm2。本晶片達到154.7dB的FoMS，在壓控振盪器感測器介面電路中達到最好的性能，同時在性能相當的狀況下，較傳統作法節省10倍的面積。

關鍵字

感測器介面電路 ； 三角積分轉換器 ； 電容耦合 ； 有限脈衝響應數位濾波器 ； 壓控震盪器 ； 節能 ； 省面積

並列摘要

In conventional sensor readout circuits, instrumentation amplifiers (IA) and analog-to-digital converters (ADC) are designed separately. The design is neither hardware nor energy efficient. The dissertation focuses on the design of ADCs which meet the analog front-end specifications for voltage sensors, and can be directly used for readout without pre-amplification. Three Continuous-Time Delta-sigma Modulators (CTDSM) with silicon proven results are introduced in this dissertation. The continuous-time architecture avoids the noise aliasing problem in discrete-time and achieves better noise-power efficiency. The Delta-Sigma structure achieves high resolution with simple low-resolution quantizers.
　　The first chip is realized in 180nm CMOS process. The structure is modified from Capacitively-Coupled Instrumentation Amplifier. By inserting a 1-bit quantizer before feedback network, Capacitively-Coupled CTDSM (CC-CTDSM) is achieved. The 1-bit implementation avoids the non-linearity problem in multi-bit feedback DAC. However, the large feedback quantization noise degrades the linearity of the Gm-C based loop filter. An FIR-DAC is implemented, acting as a low-pass filter to solve this problem, and saves significant area compared to the passive RC LPF. To stabilize the loop, the bandwidth of the loop filter should be small. We proposed the current-splitting OTA to achieve low bandwidth without large capacitor area and maintain reasonable noise-power efficiency. This work consumes 126 μW under a 1.8-V supply, achieving 75.1-dB SNDR under 80-mVpp signal and 2-kHz bandwidth. The chip area is only 0.2 mm2。
　　The second and third chips are fabricated in 40-nm CMOS process, to accommodate the need of analog circuits in advanced process for low-power IoT applications. Under the requirement of low supply voltage of 1.2 V, we use the voltage-controlled oscillator (VCO) to replace the voltage-based analog signal processing circuit to realize the senor front-end circuit. In the second work, we demonstrate an open-loop VCO-based ADC which can accommodate the sensor interface requirements. Chopping is added inside the VCO to suppress the flicker noise. The measured SNDR is 62 dB under 5-kHz bandwidth from a 8-mVpp signal The area is as tiny as 0.0145 mm2, and the power consumption is 17 μW.
Based on the first and second work, the last work of this dissertation combines the design of CC-CTDSM and VCO-based ADC. The VCO-based integrator is used to replace the Gm-C integrator in the CC-CTDSM to save the area. In another point of view, capacitively-coupled feedback architecture is used in the VCO-based ADC to improve the linearity. The input signal range is increased to 100-mVpp with 74.9-dB SNDR and -82-dB THD. The chip area is 0.06 mm2 with 21-μW power consumption. The chip achieves 154.7-dB FoMS, which is the highest among the VCO-based sensor readout circuits. The chip also achieves 10X area reduction compared to state-of-the-art conventional approach under similar performance.

並列關鍵字

Sensor Interface Circuits ； Delta-Sigma Modulators ； Capacitively-Coupled ； Finite Impulse Response Filter ； Voltage-Controlled Oscillator ； Energy-Efficient ； Area-Efficient

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