平面規劃階段電源網路的同步合成

Floorplan and Power/Ground Network Co-Synthesis

林容正(Jung-Cheng Lin)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.02306

摘要

在深次微米（DSM）技術下，金屬線（metal）長度變長並且寬度變窄，使電源導線的阻抗增大。隨著製程不斷演進，電源電壓越來越小，加上電源網路之佈局連線的電阻值所造成的電壓降（IR drop），使得供應電壓不足而導致電路功能的錯誤。因此，精確地分析電源網路是確保電路元件正常工作很重要的一環。傳統電源網路分析方法主要應用在電晶體（transistor-level）以及佈局後
（post-layout）的驗證，一但發生問題，處理上需要比較複雜的反覆修正與付出較高的成本。在本篇論文中，為了達到一次完成設計的流程（single-pass design methodology ）， 我們將電源網路電壓降的分析步驟整合到平面規劃（floorplanning）階段。我們利用電流會流向最小阻抗的特性建立一個快速分析電壓降的方法以達到平面規劃與電源網路的同步合成。最後，我們利用HSPICE
軟體來驗證我們的電壓降分析。驗證結果顯示，我們提出的快速估計電源網路電壓降模型比較於HSPICE 精準的計算電源網路電壓降之誤差最大在8%以內。透過我們的方法在平面規劃階段考量電源析，我們可以有效避免在佈局後驗證所產生的電壓降錯誤以達成一次完成設計流程的結果。

關鍵字

平面規劃階段電源網路的同步合成

並列摘要

In nanometer technology, the metal width is decreasing with the length increasing,
making the resistance along the power line increasing substantially. Thinner
wires with a lower supply voltage increase the possibility of functional failures
due to the excessive voltage (IR) drops. The voltage drop makes the supply voltage
at each gate no longer ideal. This e®ect weakens the driving capability of the gates,
increases the overall delay, and reduces the noise margin. Therefore, power distribution
analysis becomes a necessary step in ensuring the reliable operation of a design
at its intended speed. Further, the circuit sizes for high-end designs are typically
very large. The iteration cost for detecting and fixing such large-scale problems at
the end of the design flow is prohibitively high. Therefore, it is desired to develop an
e®ective methodology for design convergence. In this thesis, we present an e®ective
design methodology to integrate power/ground network analysis and floorplanning.
To make the integration feasible, we apply a very e±cient yet reasonably accurate
shortest-path modeling for power/ground analysis at the floorplanning stage. Experimental
results show that the voltage drop analysis at the floorplanning stage produces
no more than 8% error for real designs, compared to the HSPICE voltage drop
analysis. With the analysis, we can avoid the voltage drop error at the post-layout
verification stage to achieve the single-pass design methodology.

並列關鍵字

Floorplan and Power/Ground Network Co-Synthesis

參考文獻

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Representation for Non-Slicing Floorplans,” Proc. ACM/IEEE Design Automation

[5] T.-H. Chen and C.-P. Chen, “E±cient Large-Scale Power Grid Analysis Based