基於同位檢查位元預測與更正之雙對角線結構LDPC編碼器設計與實作

在本論文中，我們提出了一個對於雙對角結構之低密度奇偶校驗碼的有效編碼方法。我們所提出的編碼方法利用同位檢查位元的預測以及更正的技巧可以有效降低同位檢查位元間的資料相依性以達到縮短編碼延遲的效果。根據所提出的編碼方法我們提出兩種不同的硬體架構，其中平行編碼器可以達到較高的平行程度並且縮短編碼所花費的時間，序列編碼器則可以有效降低硬體成本。本論文所提出的編碼方法可以直接適用在IEEE 802.11n 以及802.16e 標準中所定義的低密度奇偶校驗碼。在實作結果上，我們證明所提出的硬體架構在吞吐量以及吞吐量與面積之比例方面都勝過以傳統編碼方式所得到的結果。

關鍵字

低密度奇偶校驗碼；編碼器架構；雙對角結構

並列摘要

In this thesis, an e cient encoding scheme for dual-diagonal structured LDPC codes is proposed. Our encoding algorithm employs parity bit prediction and correction to break up the data dependency within the encoding process. The parallel encoder can achieve higher level of parallelism and better hardware utilization, and the serial encoder can achieve low hardware cost. The number of required clock cycles for encoding one codeword can be reduced to achieve higher throughput performance. The proposed scheme can be directly applied to IEEE 802.11n and 802.16e dual-diagonal codes without any matrix modi cation. A low-complexity encoder architecture is proposed and implemented to verify these characteristics. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.

並列關鍵字

LDPC ； Encoding ； 802.11n ； 802.16e

參考文獻

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[8] Y. Kou, S. Lin, and M. Fossorier, Low-density parity-check codes based on fi nite geometries: arediscovery and new results," Information Theory,IEEE Transactions on, vol. 47, no. 7, pp. 27112736, 2001.

[9] T.J. Richardson and R.L. Urbanke, "Efficient encoding of low-density parity-check codes," IEEE Trans. Inform. Theory, vol.47, no.2 pp. 638- 656, Feb.2001.

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基於同位檢查位元預測與更正之雙對角線結構LDPC編碼器設計與實作

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