In SoC design, HW/SW interface design is error-prone. Different OS and bus system provide different HW/SW interface. Different IPs have different speed, data rate, throughput. Integrating them into a SoC system by hands is time-consuming and error-prone. We propose our HW/SW interface synthesis methodology for SoC design to solve this problem. Our methodology focuses on reusability, portability, and automation. We provide automation tools for bus interface synthesis and device driver synthesis. Bus interface synthesis tool improve IP integration flow, and improve IP reusability via the IP library. The data direct-connection and bottleneck detection technology are also provided to improve the system performance. The device driver synthesis tool, Expert template, can efficiently generates device driver for each IP via XML tags. The driver synthesis tool is OS independent. That means designer only need to implement one version device driver for different OS. We design some experiments to prove our methodology. The result shows our tools surely improve the SoC design.