- 學位論文
考慮光學微影效應之超大型積體電路寄生參數抽取方法
A New Lithography-Aware Interconnect Parasitic Extraction Methodology for Nanometer VLSI Circuits
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摘要
隨著IC設計的進展與IC操作頻率越來越高的進展下，IC繞線和封裝中的參數萃取已成為IC設計中非常關鍵的一個步驟。當製程技術進入100奈米以下，在同時考量蝕刻效應，光學微影效應，化學機械研磨效應等，多種效應加總而成的製程影響，並且確保時序正確已經成為一個極為困難的課題。這當中的一個主要因素來自於，IC設計者所依賴的電路圖參數萃取工具(LPE tools)，在受到種種製程因素下，在估測時序上已經變得不像以往這麼精準了。 本篇論文的研究在於探討半導體領域中，寄生參數的萃取方法。首先，我們將會先介紹IC設計的後段設計流程中，參數萃取的相關知識，這其中也包含了3D field solver和2.5D的LPE 工具，以及目前所遭受到製程因素影響而導致預估時序失準的難題。接下來我們提出一個嶄新的方法來解決有關光學微影問題所造成的RC預估失準的問題，這其中包含了光學微影效應所造成的線端退縮(line-end shortening)、線寬頸縮(Critical Dimension necking)、以及轉角圓化(corner rounding)等問題。而這個嶄新演算法不但可以融入目前標準化的後段設計流程，且可以在增加微量的計算機時間下，大幅度降低十倍左右的誤差。
並列摘要
Parasitic extraction of integrated circuit (IC) packaged and interconnect becomes a critical step because of the progress of the IC design and the increase of operating frequency. When critical dimension shrinks below 100 nanometers, ensuring timing closure against process variation is quite difficult, especially when several effect such as etch profile, lithography proximity, and Chemical-mechanical planarization (CMP) topography are lumped together. One of the main reasons is that the estimation of time delay contributed by interconnects becomes inaccurate with traditional parasitic extraction tools (LPE) which IC designers depend on. This thesis is intended as an investigation of parasitic extraction in semiconductor area. First at all, we introduce the backend flow of parasitic extraction in standard IC design, including the 3D field solver and 2.5D LPE method, and the problems suffering process effect in nanometer circuit design. Then, we propose a novel solution which incorporates lithography shape distortion effects, such as line-end shortening, Critical Dimension (CD) necking, and corner rounding. The algorithm can be integrated into a traditional standard parasitic extraction flow. The resulting estimation error reduces by ten times in average with moderate increase of computation effort.
參考文獻
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