寬能隙半導體電晶體開發:非晶態氧化銦鎵鋅薄膜電晶體與增強型氮化鎵高載子遷移率電晶體

Development of Wide-Bandgap Semiconductor Transistors: Amorphous InGaZnO Thin Film Transistors and Enhancement-Mode GaN High Electron Mobility Transistors

蘇亮宇(Liang-Yu Su)

指導教授 ： 黃建璋

國立臺灣大學/電機資訊學院/光電工程學研究所/博士(2014年)

https://doi.org/10.6342/NTU.2014.03183

摘要

本論文主要致力於發展實用寬能隙半導體材料電晶體，包含製備於玻璃基板上的低雜訊高速非晶態氧化銦鎵鋅薄膜電晶體與製備於矽基板上高壓增強型氮化鎵高載子遷移率電晶體，高速薄膜電晶體將可直接應用於製作面板驅動電路，實現面板系統整合，並且有助於發展低成本射頻識別標籤，氮化鎵高載子遷移率電晶體由於其高崩潰電壓與低導通電阻特性，將可取代現今矽材功率元件，應用於發展高頻高效率電源轉換器。
高介電係數絕緣層可有效的降低元件操作電壓以及提升元件電流密度，然其高介面缺陷與窄能隙常導致元件不穩定與較高的漏電流，為了改善這些問題，我們提出了氧化鉿/氧化矽雙層絕緣層結構，並以磁控濺鍍沉積氧化銦鎵鋅通道層，由於高介電係數能增加對載子的控制能力以達成完全空乏型操作，元件實現低次臨界擺伏 96mV/decade，高開關比達 1.5×1010，低於 50mV 的磁滯效應，在進一步的實驗中，相較單層氧化鉿，氧化鉿/氧化矽能有效增加載子遷移率、降低次臨界轉導、降低漏電流及增加元件開關比，低頻雜訊分析指出元件雜訊主要為閃爍雜訊並且來自於遷移率飄移，此外氧化鉿/氧化矽元件的雜訊規一化參數Hooge’s parameters 低達 2×10 -3，為目前玻璃基板上雜訊指數最低的氧化物電晶體。
由於非晶態氧化銦鎵鋅其擁有相對於非晶矽較高的載子遷移率，有相當多文獻在從事電路應用上的工作，然一般5 階環形振盪器操作頻率普遍低於 1MHz，由於電路架構不利於分析元件製程造成頻率響應的改進，因此本文進一步研究單一元件的高頻響應，除了探討不同氧化鉿/氧化矽結構所對應的頻率響應之外，為了使元件能承受更高的偏壓，在相同的概念之下我們製備了絕緣層為氧化鋁/氧化矽之元件，在以典型紫外光微影技術製備了閘極長度為1.5μm 下，元件的 fT 為 384MHz，fmax 為 1.06GHz，為目前玻璃基板上最高速的非晶態氧化物電晶體。
氮化鎵高載子遷移率電晶體擁有高崩潰低導通電阻等優良特性，然因其本質空乏型操作不利於電源轉換上的應用，在本文中利用 p 型氮化鎵覆蓋層，實現增強型操作，本文探討製程流程、蝕刻與退火對調整臨界電壓與操作電流之影響，除了實現操作電流為208mA/mm，臨界電壓為１.7V之增強型元件外，本文同時指出為達成穩定直流電流操作，在 60nm p型氮化鎵覆蓋層下其蝕刻窗口為 50±5nm，然為達到高崩潰電壓，準確的 55nm 蝕刻控制是必需的，在本文中的元件成功在16μm的閘汲極距離下達成 1630V 高崩潰電壓操作，建立在此基礎之上，本文同時設計不同的元件與磊晶結構以調整直流特性，其中變因包括閘極金屬、鎂離子參雜濃度、氮化鋁鎵厚度以及雙異質結構，以求滿足在不同應用下對臨界電壓、操作電流、崩潰電壓的選擇平衡。
在論文的最後開發了總寬度為30mm的多指形功率元件，分別以兩種方式達成操作電流高於6A之增強型功率元件，一為利用空乏型氮化鎵高載子遷移率電晶體串接矽功率元件，並以SO-8封裝此 Cascode架構，另一則為p型氮化鎵覆蓋層單晶片增強型架構，除了探討光罩佈局以及製程流程造成的影響之外，在雙重脈衝量測的分析上指出，由於單晶片增強型元件具有一額外p型氮化鎵蝕刻製程，其電流坍塌效應較空乏型氮化鎵元件嚴重，然在電阻負載且以1MHz方波調變之下，Cascode架構由於內部矽功率元件的米勒電容導致嚴重許多的輸入方波變形，因此在改善表面鈍化層製程之後，利用p型氮化鎵覆蓋層實線之增強型氮化鎵功率元件將為未來功率電子領域所重用。

關鍵字

氧化銦鎵鋅 ； 薄膜電晶體 ； 高載子遷移率電晶體 ； 功率元件 ； 增強型

並列摘要

This dissertation focus on developing wide-bandgap semiconductor transistors, including low-noise high-speed amorphous-InGaZnO (a-IGZO) thin film transistors (TFTs) on glass substrate and high voltage enhancement-mode (E-mode) GaN high electron mobility transistors (HEMTs). High speed TFTs can be applied to fabrication of display panel driver circuit, realizing system-on-panel and help to develop low cost radio frequency identification (RFID) tags. Due to the advantages of high breakdown voltage (VBD) and low on resistance (Ron), GaN HEMTs can potential replace Si-based power devices for high-frequency high-efficiency switching mode power supplies.
High-κ dielectrics can effectively reduce the device operation voltage and increase the current density. However, high interface state and small band-gap often induce device instability and higher leakage current. To solve these problems, an HfO2/SiO2 bilayer structure was proposed as the gate dielectric of a-IGZO TFTs. Since high-κ dielectrics can improve the maximum oxide controllable charges and achieve a fully depleted state, device can exhibit low subthreshold swing (SS) of 96mV/decade, high on-to-off ratio of 1.5×1010 and a transfer curve hysteresis lower than 50mV. Next, compared to single-layer HfO2 dielectric, it was proved that HfO2/SiO2 bilayer dielectric can effectively increase carrier mobility, reduce SS, reduce leakage current and increase current on-to-off ratio. Low frequency noise (LFN) characteristics indicate that the main noise source is flicker noise and originate from mobility fluctuation. In addition, the a-IGZO TFTs with HfO2/SiO2 bilayer dielectric can achieve a low Hooge’s parameters of 2×10 -3, which is the least noisy oxide TFTs on glass substrate to date.
Since a-IGZO can exhibit higher carrier mobility than amorphous Si, many literatures have demonstrated circuit applications. However, the typical operation frequencies of 5-stage ring oscillators are lower than 1MHz. In addition, it is hard to identify the effects of process flows to the device performance under a circuit configuration. Thus the RF performance of a single discrete device and the effect of gate dielectrics are investigated. Besides discussing the high frequency response of a-IGZO TFTs with HfO2/SiO2 bilayer dielectric, to sustain higher bias voltage, we developed Al2O3/SiO2 bilayer dielectric under the same concept. The 1.5μm gate length device can achieve fT of 384MHz and fmax of 1.06GHz, which is the fasted amorphous oxide semiconductor transistor on glass substrate to date.
GaN HEMTs have the advantages of high VBD and low Ron. However, the inherent normally-on behavior excludes GaN based HEMTs from most power electronic applications. P-GaN cap layer is demonstrated to raise the conduction band and achieve E-mode operation. Effects of process approaches、etching depth and thermal alloy temperature to threshold voltage (Vth) and operating current will be discussed. Except realizing E-mode device with operating current of 208mA/mm and Vth of 1.7V, the etching process window to achieve stable current-voltage operation was estimated to be 50±5nm for device with 60nm of p-GaN cap layer. However, a precise etching depth control of 55nm is required to achieve high VBD. A high VBD of 1630V at LGD of 16μm is successfully achieved. Base on those results, Different device and epitaxial structures were also developed to optimize the device performance, including Mo/Ti/Au gate metal, Al2O3 gate dielectric, thicker AlGaN barrier layer, different Mg concentration and double heterojunction.
At the last part, multi-finger large area power devices with total width of 30mm were developed. Two approaches were employed to realize E-mode power devices with operating current higher than 6Ampere. One is connecting depletion mode (D-mode) GaN HEMTs to Si power MOSFET and assembles this Cascode structure into a SO-8 package. The other one is p-GaN capped single chip E-mode HEMTs. Besides discussing the effects of layout and process approaches, the results of dual pulse measurements indicate that due to an additional p-GaN etching process, the current collapse effect of p-GaN capped E-mode HEMTs is severer than D-mode GaN HEMTs. However, in case of resistive load switching test with 1MHz pulse width modulation input signal, the Miller capacitance embedded in the Si power MOSFET leads to much severer input signal distortion. Thus, after improve the surface passivation process, the p-GaN capped E-mode GaN HEMTs is a promising candidate for future power electronic applications.

並列關鍵字

IGZO TFT ； GaN HEMT ； E-mode ； power electronic ； RF

參考文獻

[1] Y. Kuo, "Thin Film Transistor Technology--Past Present and Future," Electrochemical Society Interface, vol. 22, pp. 55-61, 2013.

[2] J. K. Jeong, H.-J. Chung, Y.-G. Mo, and H. D. Kim, "A new era of oxide thin-film transistors for large-sized AMOLED displays," Information Display, vol. 24, pp. 20-23, 2008.

[3] W. E. Howard, "Limitations and prospects of a‐Si: H TFTs," Journal of the Society for Information Display, vol. 3, pp. 127-132, 1995.

[5] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors," Nature, vol. 432, pp. 488-492, 2004.

[6] R. H. Doremus, Glass science: Wiley, 1994.