- 學位論文
最佳化演算法應用於時脈繞線之實現
Optimization Algorithm Applied to Zero Skew Clock Tree Implementation
摘要
本論文，在系統晶片中我們提出了一個採用了1) FED(Fitted Elmore Delay) 延遲模型所導出的非直線型的分接點，結合2)利用粒子群最佳化(Particle Swarm Optimization, PSO)演算法的優化特性，將時脈繞線的連線形狀由類H型變成類X型，找出四點的最佳分接點，達到在零時脈傾斜(Zero Clock Skew)下，有效的減少時脈繞線的總線段長和時脈延遲(Clock Delay)的目的。 我們提出「最佳化演算法應用於時脈繞線之實現」的方法，實驗證明顯示此方法，跟傳統λ-Geometry DME routing方法比較，在同樣的測試例子下，及在達到零時脈傾斜(Zero Clock Skew)下，有效的減少時脈繞線的總線段長19%~5%和時脈延遲(Clock Delay) 14%~-22%。證明了將H形狀轉成X形狀是可行的並且有效。 關鍵詞 : 時脈樹、零時脈傾斜、時脈延遲、粒子群最佳化演算法
並列摘要
In this paper in the system on chip design, we propose a method to determine a nonlinear branch connection location in the timing pulse wiring design that is 1) based on Fitted Elmore Delay model and it then combines 2) the evolution characteristics of the Particle Swarm Optimization (PSO) algorithm to change the connection topology of timing pulse wiring from H shape to X shape; it determine and finds, under the requirement of Zero Clock Skew, the best branch location in the X shape wiring. With this design it can effectively reduce the total required wire length of the timing pulse wiring and reduce the overall timing pulse delay. We propose the methodology of ‘Optimization Algorithm Applied to Zero Skew Clock Tree Implementation’ and from many test experiments under the requirement of Zero Clock Skew it reveals that our proposed design algorithm, comparing with the conventional λ-Geometry DME routing method, can effectively reduce the total wiring length of the timing pulse wiring by 5% ~ 19% and clock delay by 14%~-22% ; consequently it appears that our proposed algorithm by changing the conventional H shape into X shape in the wiring design is a realizable and effective design methodology.