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  • 學位論文

具有完整資料傳遞與預充電時間形式之新型非同步控制電路

A New Asynchronous Control Circuit with Complete Data and Precharge-Time Scheme

指導教授 : 江正雄 江正雄

摘要


在這篇論文裡,我們提出了一種可實行在非同步應用上的控制電路,叫做CDPC (Complete Data and Precharge-Time Controller),其控制線路依照4-phase signal protocol 來產生控制信號,並用來控制使用動態電路的資料路徑。比較以前的非同步控制電路,新的控制電路有著保證資料傳遞給下級的完整性以及擁有運算電路預充電時間完整性的優點。 根據此非同步電路控制器,我們以 TSMC 0.18um 的製程來設計並實現一個 8-bit 開根號處理器,此處理器操作在 VDD=3V 時,其latency 時間只需1.69 nS,運算吞吐率可至1.05 GHz,而其功率消耗則僅需0.061 nJ。 由新型非同步開根號器與傳統的同步開根號器的電路做比較,可以看出新型非同步開根號器少了級與級之間的暫存器,因此也減少了電晶體數與功耗並且增加了電路的效能 ( 速度與運算量 )。

並列摘要


This thesis present a new control circuit, CDPC ( Complete Data and Pre-charge Time Controller ), that can be used to asynchronous application, . This control circuit generates the control signal according to the 4-phase signal protocol, and can be used to control the dynamic logic in the data path. Compared with the previous asynchronous control circuits, the new control circuit has the advantages of completeness when sending data to the next stage and complete pre-charge time for the calculation circuit. Based on the new controller, we implemented an 8-bit square root circuit with TSMC 0.18um process. When VDD is at 3V, the latency is only 1.69ns and the throughput can reach 1.05 GHz. The energy consumption is only 0.061 nJ. Comparing the new asynchronous square root circuit with the synchronous type, we can see that the new asynchronous square root circuit has no latches between stages. It decreases the gate-count and power consumption, and increases the circuit efficiency (the speed and the throughput).

參考文獻


[2] C.-S. Choy, “A new control circuit for asynchronous micropipelines,” IEEE Transactions on Computers, vol. 50, no. 9, pp. 992-997, Sep. 2001.
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[4] G. Cometta and J. Cortadella, “Asynchronous multipliers with variable-delay counters,” IEEE Electronics, Circuits, and Systems, pp. 701-705, 2001.
[5] I. E. Sutherland, “Micropipelines,” Comm. ACM, vol. 32, no. 6, pp. 720-738, June 1989.
[6] P. Day and J. Viv. Woods, “Investigation into micropipeline latch design styles,” IEEE Transactions on VLSI Systems, vol. 3, no. 2, pp. 264-272, June 1995.

被引用紀錄


何孟軒(2011)。16x16位元非同步管線式系統之布式乘法器〔碩士論文,淡江大學〕。華藝線上圖書館。https://doi.org/10.6846/TKU.2011.00317

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