具快速鎖定機制之電阻式頻率鎖定振盪器設計

Design of Fast-Locking Resistive Frequency Locked Oscillator

郭蔡融(Cai-Rong Kuo)

指導教授 ： 楊維斌

淡江大學/工學院/電機工程學系碩士班/碩士(2022年)

https://doi.org/10.6846/TKU.2022.00475

摘要

隨著WSN (Wireless Sensor Network) 和IoT (Internet of Things)應用日漸增加，各項產品朝著更低體積、更低功耗的方向開發，將系統整合至同一晶片下的系統單晶片SoC (System-on-Chip)顯得格外的重要。通訊系統中，穩定的參考時脈源通常來自晶體振盪器，但體積龐大的晶體振盪器，本身不易整合於SoC中。整合於SoC的晶片內振盪器有許多架構，又以RC弛張振盪器最為常見，藉由對電容的充電，透過比較器比對參考電阻，產生電容的復位訊號，藉此來回振盪產生時脈。在此結構中，一個時脈週期是RC延遲、比較器延遲和緩衝器延遲的總和。電阻能夠藉由正負溫度係數抵銷的技巧補償，電容的溫度變化可以忽略不計，但比較器及緩衝器的溫度變異則必須使用複雜的設計技術才能夠補償，但溫度仍然是不穩定性的主要來源。
本論文提出一具快速鎖定機制之電阻式頻率鎖定振盪器。主體採用電阻式頻率鎖定迴路的架構，改善傳統RC弛張振盪器之溫度變異性及功耗取捨上的影響，能夠於溫度變異下達到穩定及有效的減少功率支出。此架構基於開關電容於固定頻率控制下可當作電阻器使用的原理，並使用低功耗放大器取代了比較器，將來源電阻與開關電容阻值相匹配，控制振盪器的輸出。對應於來源電阻值，控制開關電容達等效阻值之頻率即此振盪器輸出頻率，以此方法做為鎖頻迴路。
為了能夠壓低功耗及維持頻率長時間的穩定，設計上會採用較低頻寬操作速度較慢的低功耗放大器及較大的電容來穩定壓控振盪器輸出。這造成在一些休眠喚醒切換的應用中，振盪器需要較長的啟動時間才能達到目標工作頻率。為此，這邊提出一個能夠加速達到鎖定目標頻率的機制。此機制於電路啟動或喚醒時作動，採用加入四級額外電容並使用電荷轉移的方式將電壓控制振盪器之控制電壓進行調整，達到頻率快速推近至目標的目的，動作結束後將會停用此機制減少不必要的額外消耗。
本論文提出的電路，採用聯電UMC 0.18μm CMOS製程來實現，經模擬，在1.2V工作下，室溫下能夠輸出頻率為10 MHz，功率消耗為20.02μW，於 -40至90℃ 溫度變化下，溫度係數為20.66 ppm/℃，與無快速鎖定機制相比，減少了約1/3的追鎖時間。

關鍵字

振盪器 ； 弛張振盪器 ； 電阻式頻率鎖定 ； 快速鎖定 ； 低功耗

並列摘要

With the increasing number of WSN (Wireless Sensor Network) and IoT (Internet of Things) applications, and the development of various products in the direction of lower volume and lower power consumption, it is particularly important to integrate the system into a SoC (System-on-Chip) under the same chip. In the communication system, the stable reference clock source usually comes from the crystal oscillator, but the bulky crystal oscillator itself is not easy to integrate into the SoC. The on-chip oscillator integrated in the SoC has many structures, and the RC relaxation oscillator is the most common. By charging the capacitor, comparing with the reference resistance through the comparator, the reset signal of the capacitor is generated, thereby oscillating back and forth to generate the clock. In this configuration, one clock period is the sum of the RC delay, comparator delay, and buffer delay. The resistance can be compensated by the technique of canceling the positive and negative temperature coefficients, and the temperature variation of the capacitor is negligible. As for the temperature variation of comparators and buffers, complex design techniques must be used to compensate, but temperature is still a major source of instability.
This paper proposes a Fast-Locking Resistive Frequency Locked Oscillator. The main structure adopts a resistive frequency-locked loop structure, which improves the temperature variability of traditional RC relaxation oscillators and the influence of power consumption trade-offs, and can achieve stability and effectively reduce power consumption under temperature variability. This structure is based on the principle that the switched capacitor can be used as a resistor under fixed frequency control, and uses a low-power amplifier instead of the comparator to match the source resistance with the switched capacitor resistance to control the output of the oscillator. Corresponding to the reference resistance value, the frequency at which the control switch capacitor reaches the equivalent resistance value is the output frequency of the oscillator, and this method is used as a frequency locking loop.
In order to reduce power consumption and maintain frequency stability for a long time, a low-power amplifier with lower bandwidth and slower operation speed and a larger capacitor are used to stabilize the output of the voltage-controlled oscillator. This results in a longer start-up time for the oscillator to reach the target operating frequency in some sleep-wake-up switching applications. To address this issue, this paper proposes a mechanism that can accelerate reaching the locked target frequency. This mechanism is activated when the circuit starts or wakes up. It adopts the method of adding four extra capacitors and using charge transfer to adjust the control voltage of the voltage-controlled oscillator, so as to achieve the purpose of quickly approaching the frequency to the target. After the action is over, this mechanism will be disabled to reduce unnecessary extra consumption.
The circuit proposed in this paper is realized by UMC 0.18μm CMOS process. After simulation, under 1.2V operation, the output frequency is 10 MHz and the power consumption is 20.02μW at room temperature.Under the temperature change from -40 to 90℃, the temperature coefficient is 20.66 ppm/℃. Compared with no quick locking mechanism, the chase lock time is reduced by about 1/3.

並列關鍵字

Oscillators ； Relaxation Oscillators ； Resisive Frequency Locked ； Fast Locking ； Low Power

參考文獻

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