佈局對高壓靜電防護能力影響與驗證

To Verify the Effect upon the Device’s ESD When Modifying the HV MOS Layout

張純(Chun Chang)

指導教授 ： 李揚漢

淡江大學/工學院/電機工程學系碩士在職專班/碩士(2009年)

https://doi.org/10.6846/TKU.2009.01341

摘要

本篇摘要未授權

關鍵字

靜電放電 ； 人體放電模式 ； 機器放電模式 ； 傳輸線觸波產生器

並列摘要

This abstract would not be displayed due to no authorization.

並列關鍵字

ESD ； HBM ； MM ； TLP

參考文獻

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[7] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, vol. 46, pp. 173-183, 1999.

[11] C. H. Dfaz, T. E. Kopley, and P. J. Marcoux, "Building-in ESD/EOS reliability for Sub-Half micron CMOS Processes," IEEE Transactions on Electron Devices, Vol. 43, No. 6, pp. 991-999, June 1996.

[12] C. Duvvury, et al., “Achieving uniform nMOS device power distribution for sub-micron ESD reliability,” in IEDM Tech. Dig., pp.131-134, 1992.

[13] T.-Y Chen and M.-D. Ker, “ Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices,” in IEEE Trans. on Device and Material Reliability, vol. 1, no. 4, pp.190-203, 2001.