應用於音頻之極低電壓多位元三角積分調變器

An Ultra Low-Voltage Multibit Delta-Sigma Modulator for Audio-Band Application

謝懷娟(Huai-Juan Xie)

指導教授 ： 郭建宏

淡江大學/工學院/電機工程學系碩士班/碩士(2008年)

https://doi.org/10.6846/TKU.2008.01022

摘要

本篇論文主要是在描述運用在0.18μm CMOS制程下，設計ㄧ個應用於音頻之極低電壓多位元三角積分調變器。本篇應用於雙取樣技術，始時脈可以被更有效的運用，並減輕運算放大器在設計上的困難。在本篇論文中我們也設計的一個新的低電壓多位元比較器，有別於傳統的電阻分壓法，減少不必要的靜態功率的消耗。
應用於音頻之極低電壓多位元三角積分調變器所達到的SNDR為88dB，而他的動態範圍為89dB，當基頻為22.05KHz，輸入頻率為88dB，而他的動態範圍為89dB，輸入頻率為1.25KHz。當供應電壓為0.8V時，所消耗的能量為4.2mW。

關鍵字

多位元量化 ； 多位元量化器 ； 三角積分調變器

並列摘要

This paper presents a 0.8 V multibit delta-sigma (ΔΣ) modulator with a single switched-opamp (SOP) in a 0.18 μm 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed.
The presented ΔΣ modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.

並列關鍵字

multibit ； multibit quantizer ； Delta-Sigma modulator

參考文獻

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[3] M. Steyaert, J. Crols, and S. Gogaert, “Switched-opamp: a technique for realizing full CMOS switched-capacitor filters at very low voltages,” in Proc. 19th Eur. Solid-State Circuits Conf., pp. 178–181, Sep. 1993.

[4] V. S. L. Cheung, H. C. Luong, and W. H. Ki, “A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter,” IEEE J. Solid-State Circuits, vol. 36, pp. 14–22, Jan. 2001.

[5] S. Rabii and B. A. Wooley, “The design of low voltage, low power sigma delta modulator,” Kluwer academic pulisher, 1999.