低複雜度之四路徑動態可重組 MDC FFT 處理器設計

在通訊系統中，垂直正交頻率多工(OFDM)被大量的使用在不同的通訊協定中，而快速傅立葉(FFT)在OFDM系統中占有相當重要的角色，負責將調變後的資料從時域轉為頻域。此篇論文提出了四路徑FFT延遲交換架構(MDC)，多路徑之FFT處理器相較於傳統的單路徑架構其資料吞吐量較大，在資通訊發達的現今也較能符合處理大量的資料需求，並將在同一點數FFT運算中重複的迴旋因子(Twiddle Factor)提取出來，再利用三角函數之值互補原理簡化迴旋因子所佔用的面積，而迴旋因子能由右移位電路達成，取代面積較大的乘法器，因此降低了FFT處理器的複雜度。而不同的通訊協定所應用的FFT點數也不同，本實驗使用FPGA的部分動態可重組(PDPR)技術能夠在不同時間點切換不同電路的優點，使得在架構設計上更具有彈性，此處理器以64點FFT作為靜態區的電路，將其它的點數規劃為可重組模組(RM)，系統能夠在不同環境參數下切換64到512點運算電路，若欲加入更高的點數僅需將新電路加入新的RM，便能達到應用需求，而使用PDPR技術也降低了電路所佔用的硬體資源。從實驗結果得知，此論文所提出的設計方法提升了FFT處理器之資料吞吐率，在硬體資源比較方面，平均減少了 26.5% slice 與 46.56% flip-flops 的使用率。

關鍵字

垂直正交頻率多工；快速傅立葉；部分動態可重組

並列摘要

Nowadays, Orthogonal Frequency-Division Multiplexing (OFDM) is widely used in different communication protocols. Fast Fourier Transform (FFT) plays an important role in OFDM system. This work proposed a 4-path Multipath Delay Commutator (MDC) which increase throughput of FFT processor compare with traditional single path FFT architecture, and propose a method of reducing Twiddle Factor (T.F.) computational circuit area by using trigonometric complementary theorem. The twiddle factor computational circuits can be reached by a right shift circuits, which reduced the design complexity. But different protocols use different FFT-Point. Partial Dynamic Reconfiguration (PDR) capable of switching time-independent circuits, which increase the flexibility of system design. This FFT processor used 64-Point FFT as a static area circuit, and configured other FFT Points as Reconfigurable Modules (RM). System can configure 64 to 512-Point under different environment. And using PDR also reduced the occupied hardware resources. From experimental results shown that use proposed methodology can increase the throughput of FFT processor, and average reduce 26.5% slice and 46.56% flip-flops utilization.

並列關鍵字

OFDM ； Fast Fourier Transform ； Partial Dynamic Reconfiguration

參考文獻

[1] K. J. Yang, S. H. Tsai, and G. C. H. Chuang, “MDC FFT/IFFT processor with variable length for MIMO-OFDM systems,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 21, Issue. 4, pp.720-731, Apr. 2013.

[3] B. Kang and J. Kim, “Low complexity multi-point 4-channel FFT processor for IEEE 802.11n MIMO-OFDM WLAN system,” in Proc. of IEEE Int. Sym. on Green and Ubiquitous Technology (GUT), Jul. 2012, pp. 94-97.

[5] J. W. Cooley and J. W. Tukey, “An Algorithm for the Machine Calculation of Complex Fourier Series,” in Proc. of Mathematics of Computation, vol. 19, pp. 297-301, Apr. 1965.

[6] E. J. Kim and H. S. Myung, “High speed eight-parallel mixed-radix FFT processor for OFDM systems,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2011, pp. 1684 - 1687.

[7] S. Yoshizawa, A. Orikasa, and Y. Miyanaga,“An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2011, pp. 2705-2708.

國際替代計量

低複雜度之四路徑動態可重組 MDC FFT 處理器設計

未授權

主題瀏覽