- 學位論文
單層/多層原子晶片的開發與製作應用於原子物理領域
Development and Fabrication of Single / Multi-layer Atom Chips for Applications in Atomic Physics
摘要
在玻色-愛因斯坦冷凝聚理論被實現後，使用微影的技術來定義出微細的導線，通入電流後產生所需的磁場梯度，並與外加均勻磁場相互抵銷出磁場空缺以拘束被雷射冷卻後的中性原子(neutral atoms)。在本論文中，首先利用微機電的技術與電鍍銅的金屬化製程來製作出單層原子晶片，取代了傳統龐大的線圈而縮小到2.5cm2的晶片上。原子晶片表面將做為冷卻原子之雷射光的反射，所以提高表面反射率也是本論文之另一研究重點。經過高電流測試單層原子晶片100μm寬與13μm高的導線之極限電流密度可達到(6.67×105 A/cm2)。 一般單層原子晶片對於導線圖型的限制很多，然而多層原子晶片在導線圖型設計的彈性上又更加廣泛，增加了原子晶片的應用範圍。本論文選用負光阻SU-8作為層與層之間的絕緣平坦層，但是SU-8屬於高分子聚合物，此材料導熱係數很差因而阻礙上層導線的散熱，導致上層導線(100μm寬)之極限電流密度降低，減少導線能夠承受的電流值與電流通過的時間，無法達到原子物理實驗的需求，所以我們在製作原子晶片時加入了散熱的設計，與無散熱設計的極限電流密度(2.44×105 A/cm2)相比，其上層導線的極限電流密度可以提高55.7% 達到3.8×105 A/cm2。本論文在製作多層原子晶片時加入化學機械研磨拋光的製程，來整平SU-8在旋轉塗佈時受到底部結構影響所產生的表面紋路，並且降低表面粗糙度(Ra)達到5nm。電性測試結果顯示，上層導線可以承受超過5安培的電流通過，並且持續5分鐘未燒斷，因此確定本論文所提出的多層原子晶片足以滿足原子物理的實驗。
並列摘要
After Bose-Einstein condensates (BEC) is realized. Lithographically fabricated circuit patterns can provide magnetic gradient with bias magnetic field to generate microtraps for trapping cold neutral atoms. In this thesis, MEMS and copper metallization technology was employed to fabricate single layer atom chips to replace the traditional large coils, in which the total area can be reduce to 2.5cm2 on the chip. The chip surface roughness was also examined for reflecting the laser beam for the purpose of laser cooling, and thus the improvement of the surface roughness was studied in this thesis. The test results show the measured current density of wires (100μm wide and 13μm thick) of single layer atom chips is 6.67×105 A/cm2. Generally, The single layer atom chip has many restrictions on the magnetic trap but multilayer atom chips offer more flexibility on designing magnetic traps. In this thesis SU-8 was chosen as the isolation layer in between upper wires and bottom wires. However, photoresist SU-8 is a polymer material and its thermal conductivity is very poor that reduces the maximum current density (2.44×105 A/cm2) of upper wires (100μm wide). The heat dissipation copper blocks were incorporated in our chip design to increase the sustainable current densities of upper wires of more than 3.8×105 A/cm2(Improved by 55.74%). The SU-8 thickness, surface flatness and roughness (Ra = 5nm) were controlled by the CMP process. From our electric current and lifetime test results, more than 5 Amps of current can be successfully run through upper copper wires for at least 5 minutes without burnout. Therefore, all of the tested wires were suitable for chip-based atom trapping experiments.