不同溫度及閘極/汲極偏壓對氫化非晶矽薄膜電晶體之可靠度分析

現今氫化非晶矽薄膜電晶體(a-Si:H TFTs)已被廣泛應用於各式液晶顯示器中，但其可靠度問題，尤其是高溫的變化，仍有探討的空間。可靠度問題中，不同閘極與汲極偏壓下，電晶體的劣化機制仍不明確，其適用的模式也有待建立，這也是本研究的動機。　　本研究採用凌巨交錯型基底之薄膜電晶體做為樣本，分別在25、75、125℃溫度下，以閘極與汲極定電壓應力(constant voltage stress, CVS)的方式，做可靠度測試，量測電晶體特性，分析其劣化情況，探討閘極介電層與通道表面的劣化機制。另外為模擬實際操作情況，本研究也採用AC信號，進行應力測試。　　經由實驗結果發現，在高溫及較高的閘極應力電壓下，元件劣化較嚴重，經過閘極與汲極的加壓測試之後，隨著汲極偏壓的增加，劣化會有減緩趨勢，推估主要是由於閘極與汲極相對電場減少，如同對閘極做負偏壓應力測試，使通道上的缺陷減少，ΔVt與汲極電流退化隨之減少。當VD接地VG為操作電壓在溫度為125℃的環境下做應力測試，Ion劣化最為嚴重(≒70%)，但隨著VD增加，ΔS化也會隨之減少至0.15V/dec。ΔVt也會由原本的8 V降至6V。在交流閘極應力測試下，在高頻和高工作週期，劣化較為嚴重，推測為載子沒有足夠時間離開缺陷內，造成缺陷內載子增加影響劣化。

關鍵字

閘極應力；汲極應力；氫化非晶矽薄膜電晶體；臨界電壓；溫度影響

並列摘要

The hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been widely studied. For the reliability, it still has space to explore especially in high temperature. For various gate/drain biases, the degradation mechanisms of the TFT are not clear, and no suitable model exists. That is the motivation of this study. In this study, the tested TFTs are inverted staggered type and fabricated in Giantplus Technology Corporation. The reliability tests are executed with constant voltage stress (CVS) by various gate/drain biases at temperatures of 25, 75, and 125℃.We also measure the TFT characteristics and investigate the degradation mechanisms in gate insulator and channel interface. To simulate the real operation of the TFTs, the tests in AC condition is also performed. From the experimental results, the degradation becomes more serious under high gate stress voltage and temperature. When the drain stress voltage increases, the degradation decreases slightly. We infer that the electric field near the drain decreased the effect of the gate voltage stress, it likes to set a stress of negative gate bias. The threshold voltage shift and drain current degradation decreased with increasing drain stress voltages. For applied operation voltage to the gate and VD=0 stress at 125℃, the Ion degradation is obviously (about 70%). The ΔVt decreases from 8 V to 6V and ΔS decreases to 0.15V/dec with increasing the drain stress voltage.　For the AC gate bias stress, the degradations are more serious with higher frequency and duty ratio. It might be the carriers have no enough time to de-trapped from the gate insulator and degrade more seriously with increasing carriers.

並列關鍵字

Gate stress ； Drain stress ； amorphous silicon thin film transistor (A-Si TFT) ； threshold voltage ； temperature effect

參考文獻

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[2] P. G. Le Comber and W. E. Spear, “Electronic transport in amorphous silicon films,” Phys. Rev. Lett., vol. 25, no.8, pp.509-511, Aug. 1970.

[3] W. E. Spear, R. J. Loveland, and A .Al-Sharbaty, “The temperature dependence of photoconductivity in a-Si,” J. Non-Cryst. Solids, vol. 15, pp.410-422, 1974.

[4] C. V. Berkel and M. J. Powell, “Resolution of amorphous silicon thin-film transistor instability mechanisms using ambipolar transistors,” Appl. Phys. Lett.51, pp.1094-1096, Oct. 1987.

[6] I. Chen, “The interface and the field effect in thin-film transistors,” J. Appl. Phys., vol. 56, pp. 396-400 (1954).

國際替代計量

不同溫度及閘極/汲極偏壓對氫化非晶矽薄膜電晶體之可靠度分析

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