結合分層及交錯式均等錯誤保護架構於 H.264 視訊傳輸之晶片設計

Chip Design for H.264 Compressed Video Employing Layer and Interleaver EEP

張瑋玲(Wei-Ling Chang)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2008年)

摘要

在最新的H.264視訊壓縮標準中，擁有著高影像品質跟壓縮率的特性，然而在通訊傳輸之下容易受到外在的雜訊干擾。因此本論文提出分層交錯式均等錯誤保護(Layer-Interleave Equal Error Protection，LIEEP)的方法，利用分析H.264位元流(bitstream)的重要性，將H.264位元流區分成兩個層級並相互交錯，借此避免叢聚錯誤(Burst Error)的發生，進而改善影像的品質。
實驗結果顯示，與傳統式均等錯誤保護(Equal Error Protection，EEP)比較，在相同的碼率之下，兩者所使用的頻寬幾乎相同，在SNR為5dB時，採分層交錯式均等錯誤保護的H.264視訊品質可提高2.54dB。在驗證上我們採用Xilinx Vertix-4 FPGA來驗證其正確性，並以TSMC 0.18μm 1P6M CMOS製程來完成一個分層交錯編解碼器的晶片設計，其工作頻率為200MHz，整個晶片含I/O PAD的面積為2.01 × 2.43 mm2，分層交錯解碼器的面積為2.42 × 2.02 mm2 。

關鍵字

分層交錯編碼 ； 均等錯誤保護 ； H.264/AVC ； 低密度同位檢查碼

並列摘要

The video compression standard H.264 is an efficient coding technique for video applications, but H.264 bitstream is sensitive to errors which occurs in the transmission of data. In this thesis, a new layer-interleave equal error protection scheme is proposed. Basically, we analysis the significance of the H.264 bitstream to separate into two different levels and interlace bitstream to avoid the occurance of the burst error to improve the performance of video quality.
Experiment results show that this new error protection method, under the same code rare and almost the same bandwidth, the PSNR performance of the proposed architecture can improve to the value of 2.54dB when the SNR is 5dB. Xilinx Vertix-4 FPGA is used to verify the proposed architecture. Finally, the proposed Layer-Interleaver encoder and Layer-Interleaver decoder are designed by using TSMC 0.18μm 1P6M CMOS process. The operation frequency of these chips is 200MHz. The chip size including I/O PAD of the Layer-Interleaver encoder is 2.01 × 2.43 mm2 and the Layer-Interleaver decoder is 2.42 × 2.02 mm2 .

並列關鍵字

Layer-Interleave Coding ； Equal Error Protection ； H.264/AVC ； LDPC

參考文獻

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