- 學位論文
可變距離液晶顯示器視訊格式轉換晶片之設計與製作
Design and Implementation of the Warp Distance LCD Scaler
摘要
即時數位動態影像縮放，應用在解析度的轉換，因為影像顯示直接關係到人類視覺的感受，所以在處理縮放的時間上，必須要有嚴格的規範，而不同的影像解析度規格，控制影像輸出的垂直與水平同步訊號也都有固定的頻率，因此在選用硬體電路設計演算法時，處理時間必須要符合硬體解析度的規格為最重要的準則，才不會導致輸出資料與時脈不同步，而發生錯誤。良好的演算法，必需從電路的低複雜度、低記憶體存取與高水準畫面輸出品質中，取得一定平衡點，在可允許的規格內，表現出高標準的影像縮放輸出。 在本篇論文中，採用適應性正交內插法(Adaptive normal interpolation)，針對影像邊緣區域，放大後產生的毛邊(burring)、格子(blocking)、混疊(aliasing)等情況，做視覺最佳化處理，也成功的應用並完整的實現，低複雜度電路與輸出品質良好的即時數位影像縮放硬體架構，輸出解析度最高可支援至UXGA(1600 x 1200, 60Hz)。爲了提高電路工作速度，在核心計算電路上採用暫存器儲值表，事先儲存計算參數，運算時只要適時的讀出給需要的電路，就可以減少電路複雜度，提高工作效率。硬體實現採用Verilog硬體語言來撰寫，再透過可規劃邏輯陣列(FPGA)來驗證結果。
並列摘要
Real time dynamic image interpolation has been applied in resolution transition. Because of the human vision, the time of image scale process has the strict definition. According to resolution requirement, the horizontal and vertical synchronous signals operate with different frequence standards within the LCD driving system. After the scaled algorithm has been selected for hardware design, the most important thing is to set the calculational time which is decided with the monitor resolution. If the caculational time is out of monitor scan time, the displayed image will be wrong. The suitable algorithm is selected based on the low complexity, the small memory and the high quality. In this paper, we propose a real time image scaler circuit that not only has high performance, but also has fast calculation by using ROM table. Note that the proposed circuit can support the resolution up to UXGA(1600x1200 60Hz). Furthermore, the Verilog codes must be verified with FPGA hardware. After both RTL simulation and the Gate-level simulation have been completed, the designed source codes can be made as an ASIC.