可控式共焦平面陣列讀出電路與鋰離子電池充電器之設計

此論文提出並實現一新式鋰離子電池充電器，以及一積分時間可控式的讀出電路(readout circiut)設計，可做共焦平面陣列之應用。此新式小型之鋰離子電池充電器是利用充電幫浦(charge-pump)的技術來製作，以簡單的電路架構設計成很小的晶片面積。此外，它可提供基本的電壓/電流偵測功能，充電截止偵測功能以及可自動控制充電速度的功能。此充電器在雙模式(dual-mode)下操作，並可操作在不同電流大小之定電流模式(large/trickle constant-current mode)及定電壓模式(constant-voltage mode)之不同充電速率做充電。此充電器輸出電壓可達4.2伏特，最大充電電流可達700mA。功率效率為67.89%，837mW的晶片功率消耗(power dissipation)且含晶片接腳面積僅達1.455 × 1.348mm2。此論文中所提出之另一個電路是一種可控式讀出電路可結合32 × 32砷化銦鎵偵測陣列之電路。此讀出電路是為用於砷化銦鎵感光二極體陣列偵測器所設計，可操作在低的輸入電流且適用於近紅外領域的共焦平面陣列上。讀出電路的積分時間可藉由一個外部脈波做控制，可調範圍最小為0.5μsec，根據光強度的變化做調整。此外，讀出電路的前級是使用緩衝閘調變輸入式(buffer gain modulation input)結構加上差動架構及雙三角取樣電路(double delta sampling circuit)技術實現，可提供較好的靈敏度，較寬的動態範圍，較高的注入效率和減少雜訊。更進一步來說，因為此讀出電路在每個單一像素電路中均加入取樣電路(sample-and-hold)，因此它可以操作在快攝的模式(snapshot mode)。所提出的讀出電路擁有1024個像素，而每個像素的距離為30μm。讀出電路的輸出擺幅可超過2.2伏特。非線性度為±5%，晶片功率損耗為91.559mW，而晶片面積不含輸出入接腳時為1.628 × 2.341 mm2。這二個電路均採用台積電0.35μm CMOS 5伏特製程製作實現。

關鍵字

鋰離子電池；充電器；讀出電路；砷化銦鎵光二極體

並列摘要

In this thesis, a new compact CMOS Li-Ion battery charger and a controllable integration time readout circuit(ROIC) for focal plane array(FPA) applications are presented. A new compact CMOS Li-Ion battery charger uses a charge-pump technique with a small chip size and a simple circuit structure. Additionally, it provides basic functions with voltage/current detection, end-of-charge detection, and charging speed control. This charger operates in dual-mode and is supported in the trickle/large constant-current mode to constant-voltage mode with different charging rates. This charger output voltage reaches 4.2V, and the maximum charging current reaches 700mA. It has 67.89% power efficiency, 837mW chip power dissipation, and only 1.455 × 1.348 mm2 in chip area including pads. Another proposed circuit in this paper is a controllable readout circuit with a 32 by 32 Indium Gallium Arsenide (InGaAs) detector array. This ROIC is designed for InGaAs photodiode(PD) array detectors to operate at low input current and is suitable for the focal plane array(FPA) in near infrared(NIR) field. The integration time of this ROIC can be controlled by an external clock pulse, and is adjustable from 0.5μsec to infinity by varying the light intensity. Moreover, the pre-stage of ROIC is based on the buffer gate modulation input (BGMI) architecture with differential structure and a double delta sampling(DDS) circuit, providing better sensitivity, a wider dynamic range, a higher injection efficiency, and reduced noise. Further, because this ROIC is built into a sample-and-hold circuit in the unit cell, it can operate in the full frame snapshot mode. The proposed ROIC has 1024 pixels and a 30μm pixel pitch. The ROIC output swing is over 2.2V. It has ±5% non-linearity, 91.559mW chip power dissipation, and a chip area of 1.628 × 2.341 mm2 without pads. These two circuits are implemented using TSMC 0.35μm CMOS process with a 5V power supply.

並列關鍵字

Li-ion battery ； charger ； readout circuit ； InGaAs photodiode

參考文獻

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[2] C. C. Hsieh, C. Y. Wu, T. P. Sun, F. W. Jih, and Y. T. Cherng,” High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA,” IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1188-1198, Aug. 1998.

[3] T. H. Yu, C. Y. Wu, P. Y. Chen, F. W. Chi, J. J. Luo, C. D. Chiang, and Y. T. Cherng, ”A new CMOS readout circuit for uncooled bolometric infrared focal plane arrays,” IEEE International Symposium on Circuits and Systems, pp. 493-496, May 2000.

[4] Y. C. Shih, and C. Y. Wu, “An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications,” in IEEE International Symposium on Circuits and Systems, pp. 809-812, May 2003.

[5] Y. C. Shih, and C. Y. Wu, “A New CMOS Pixel Structure for Low-Dark-Current and Large-Array-Size Still Imager Applications,” IEEE Trans. on Circuits and Systems-I: Reg. Papers, vol. 51, no. 11, pp. 2204-2214, Nov. 2004

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可控式共焦平面陣列讀出電路與鋰離子電池充電器之設計

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