射頻低雜訊放大器與高線性降頻式混頻器研製

Design and Implementation of Radio-Frequency Low-Noise Amplifier and High-Linearity Down-Conversion Mixer

洪郁鈞(Yu-Jun Hong)

指導教授 ： 黃育賢 ； 陳建中

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2013年)

摘要

本論文是以TSMC 0.18 um CMOS製程，研究一個超寬頻低雜訊放大器、雙頻帶低雜訊放大器及一個以TSMC 90 nm CMOS製程研究一個高線性降頻式混頻器為研究目標。研究主題分為三大部分:
第一個部份為一個可應用於超寬頻接收機系統之3.1~10.6GHz的低雜訊放大器主要使用了電感峰值(inductive peaking)技術來完成，第一級電路主要使用電流重複利用(current reuse)的技術來增加電路增益，第二級放大器主要將傳統的電阻分流回授放大器中加入兩個電感，閘極端的回授電感會和電晶體的寄生電容cgs共振，可以降低雜訊指數，汲極端的電感可以增加高頻增益，增加增益平坦度。利用此技術，電路最大增益為9.61dB，-3dB頻寬為0.5~6GHz，雜訊指數為6.5dB以下，輸入三階諧波截止點約為-11dBm，直流功率消耗為9.5mW，其晶片面積為1.04 mm2。
第二部分為研究一個可應用於2.4、5.2GHz兩個頻段的雙頻帶低雜訊放大器。為了達到雙頻段同時匹配的效果，輸入匹配主要採用二個極點(two poles)的匹配方式，輸出端則是採用電感電容串聯及並聯共振的方式，來達到雙頻段同時匹配。由於輸出端的匹配方式會使原本電路最高增益受到限制，為了改善此問題， 我們使用一個增益提高的方法，可以讓雙頻帶低雜訊放大器在不增加太多功率消耗的情況下來達到增益提高的效果。電路最大增益為12.9、8.2dB，雜訊指數為3.7、3.7dB，輸入三階諧波截止點約為-4、-1dBm，直流功率消耗為7.8mW，其晶片面積為1.13mm2。
論文最後為使用TSMC 90 nm CMOS製程，完成一個高線性降頻式混頻器，由於在4G LTE發射機中，需要一個高線性度的正交解調變器。因此，在設計正交解調變器中的子電路混頻器時，主要將傳統的吉伯特混頻器做改良。改良後之混頻器具有增益控制的功能，當混頻器切換為低增益模式時可以增加電路的線性度。LO開關的四顆電晶體操作在次臨界區(subthreshold)可以減少消耗功率。電路最大轉換增益為6.93dB，輸入三階諧波截止點為5dBm，功率消耗為5.02mW，其晶片面積為0.95 mm2。正交解調器使用高線性降頻式混頻器來完成，模擬結果為振幅誤差小於0.1dB、相位誤差小於0.5度。功率消耗為10mW。

關鍵字

低雜訊放大器 ； 電流重複利用 ； 電感峰值 ； 降頻式混頻器 ； 正交解調變器

並列摘要

This study is to design an ultra-wideband low noise amplifier, a dual-band low noise amplifier, and a high-linearity down-conversion mixer, which are implemented with TSMC 0.18 um CMOS technology and TSMC 90 nm CMOS technology.
The first part is a receiver system for ultra-wideband low noise amplifier. It mainly uses the inductive peaking techniques. The first stage circuit uses current reusing technology to increase the circuit gain. The second stage amplifier is based on the traditional resistive shunt feedback amplifier and adds two inductors. Gate feedback inductor resonates with parasitic capacitor (Cgs) of MOSFET to reduce the noise figure. The additional inductor increases high frequency gain and gain flatness. Using this technique, the circuit maximum gain is 9.61dB, -3dB bandwidth is 0.5 ~ 6GHz, noise figure is less than 6.5dB, input third order intercept point (IIP3) is about -11dBm, DC power consumption is 9.5mW, and chip area is 1.04 mm2.
The second part is a study of dual-band low noise amplifier, which can be applied to both 2.4 and 5.2 GHz bands. In order to achieve concurrent dual-band characteristics, we use two poles matching at input terminal and use inductive capacitors in series and parallel resonance at output terminal to achieve the dual-band simultaneously match. Since the matching mode of the output terminal, the maximum gain of the circuit will be limited. To overcome this problem, we use a method without increasing power consumption to improve dual-band low noise amplifier gain. The maximum gain of the proposed circuit is 12.9 and 8.2 dB, noise figure is 3.7 and 3.7 dB, input third-order harmonic cutoff point is about -4 and -1dBm, DC power consumption is 7.8mW, and the chip area is 1.13mm2.
Finally, we have completed a high-linearity down-conversion mixer using TSMC 90 nm CMOS process. In 4G LTE transmitter, we need a high-linearity quadrature demodulator. Therefore, in the design of quadrature demodulator, we improved the traditional Gilbert mixer. The proposed mixer has gain control functions. When the mixer is in low gain mode, it can increase the linearity of the circuit. In switch stage (LO), the MOSFETs operate in subthreshold region, which can reduce power consumption. The maximum conversion gain is 6.93dB, input third order harmonic intercept point is 5dBm, power consumption is 5.02mW, and the chip area is 0.95 mm2. The quadrature demodulator uses high-linearity down-conversion mixers. Simulation results show that the amplitude error is less than 0.1dB, the phase error is less than 0.5 degree, and the power consumption is 10mW.

並列關鍵字

Low-Noise Amplifier ； current reuse ； inductive peaking ； Down-Conversion Mixer ； quadrature demodulator

參考文獻

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