供行動裝置之新型重置信號晶片設計

New design for a reset IC of mobile device

林敬傑(Ching-Chieh Lin)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2008年)

https://doi.org/10.6841/NTUT.2008.00225

摘要

由於行動裝置之系統設計複雜度越來越高，系統設計者所需之電源時序控制也就越來越重要。未經規劃之電源起動順序(POR, Power-on Reset)可能導致系統不穩或不開機，因此，本論文提出一種新型重置信號晶片架構設計以解決電源上升(ramp-up)之時序問題。在系統設計上，主要由以下各電路組成，磁滯輸入電壓、電源延遲控制、輸出致能接腳、電源良好(Power Good)信號、低電壓重置電路(Low Voltage Reset Circuit)。最後，採用TSMC 0.35um 2P4M之製程實現。實驗結果顯示在輸入電源3.3V +/- 10%、類比輸入信號1.5V~5V、磁滯輸入電壓15~30mV、低電壓重置之啟動電壓2.7~2.8V等條件下，此一晶片功率消耗為40mW，其輸出為0~3.3V。

關鍵字

電源起動順序 ； 上升 ； 電源良好 ； 低電壓重置電路

並列摘要

Because the complication of system design in a mobile device has already became more and more difficult, the need for system designers to control power sequence has also became more and more important. A planless POR may lead to system unstable or hang during the boot. Therefore, the thesis provide a new reset IC structure to solve the sequence problem during power ramp-up here. For system design, this chip contains hysteresis input voltage, power delay control, enable output, power good signal, and LVRC. Finally, it is implemented using TSMC 0.35um 2P4M process. Experiment result are shown here when we set 3.3V +/- 10% as input power, 1.5~5V as analog input signal, 15~30mV as hysteresis input voltage, and 2.7~2.8V as startup voltage of low voltage reset circuit. The chip consumes 40mW power and output voltage range is around 0~3.3V.

並列關鍵字

POR(Power-on Reset) ； ramp-up ； Power Good ； LVRC(Low Voltage Reset Circuit)

參考文獻

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