晶片型DNA定量分析儀器已經廣泛應用於各種醫療檢測與基因研究,在未來甚至可實現居家照護(Point of Care, POC)應用檢測,而在這種場合儀器無法定期校準與維護,因此可靠度成為儀器是否能穩定運作並發揮檢驗功能的關鍵因素。 本研究建立即時偵測同步定量聚合酶連鎖反應器之系統模型,透過數值實驗,評估儀器之設計,並藉由模型分析DNA定量實驗之結果,建立一套系統方法來實現晶片型即時偵測同步定量聚合酶連鎖反應分析儀器(Real-Time PCR)之強健設計。 強健設計五項主要工具︰理想機能數學函數用於表示指定信號之反應關係;因子分析圖(P-Diagram),劃分噪音、控制、輸入與輸出因子;二次損失函數用來量化偏離目標之機能;信噪比,可透過實驗來預估設計特性;直交表,可收集提昇可靠度之設計參數,規劃最少量之實驗。 加速壽命試驗(Accelerated Life Test, ALT),用來評估儀器之可靠性,根據壽命試驗之規劃,模擬晶片型即時偵測同步定量聚合酶連鎖反應分析儀器連續工作三年以上之測試,測試結果驗證,該即時偵測同步定量聚合酶連鎖反應分析儀器經過三年的運作後,進行DNA定量實驗仍具有高重現性,這不僅證實晶片系統之強健性,更驗證強健設計系統方法為一有效之方法。
Chip-based DNA quantification system will be wide spreading and even applied to point-of-care applications. Applying for such status, the instrument may not be maintained or calibrated regularly. The machine reliability is a key issue for normal operation. In this study, a system model of the real-time PCR (Polymerase Chain Reaction) machine was build to evaluate the instrument design through numerical experiments. A systematic approach was developed to achieve the robust design of a real-time PCR on chip system for high reproducibility of DNA quantification based on model analysis results. The robustness strategy uses five primary tools: Ideal function used to specify mathematically the signal-response relationship; P-Diagram (Parameter diagram) classifies the variables into noises, control, signals, and response factors; Quadratic loss function to quantify the deviation from target performance; Signal-to-noise ratio is used for predicting the design quality through laboratory experiments, and orthogonal arrays are used for gathering dependable information about design parameters with a small number of experiments. Accelerated lift test (ALT) was adopted to evaluate the reliability of the prototype. According to the simulated life test plan, this real-time PCR on a chip system was simulated to work continuously for over three years. The ALT tests show that the real-time PCR machine will have the similar reproducibility on DNA quantification even after three year operation. That not only shows the robustness of the on-chip system but also verifies the effectiveness of the systematic method to achieve robust design.