整合可製造性設計方法於X時脈樹

隨著製程科技的日新月異，製程元件的微小化賦予超大型積體電路製造極大的整合力，原先許多電子產品需靠繁雜電子電路與元件組成的，現今在奈米製程上都可很輕易的將整個系統整合在一顆晶片上。然而奈米製程卻深受電路效能與良率不佳的窘境，深究其因乃製程上的一些缺失諸如光學微影、新製程物質缺陷所致，因此可製造性設計的議題對於積體電路設計者與電子設計自動化為必須考量的關鍵因素。目前針對實體設計上考量可製造性設計的文獻已於近來急速增加，然對於時脈繞線上仍未有著墨，而已提出的繞線方法也難以整合於時脈繞線上。為此，本文提出金屬線段層次安排的方法，藉由衝突圖形的建立與尋求每一層金屬線段的最大獨立解，於X時脈繞線後改善光學鄰近上線段過近及減少穿孔點數量來提升良率與可靠度。實驗數據顯示此法可有效解決線段重疊與線段過近的問題並減少79.12%的穿孔點數量，除此之外，本文亦針對此法產生的副作用提出因應之法並對於可製造性設計提出一套整合之架構。

關鍵字

可靠性設計；非曼哈頓繞線；零時脈偏差；時脈樹；光學鄰接校正；冗餘穿孔點； X時脈樹

並列摘要

As the advanced process and shrinking feature size integrate more and more functions on one chip, accompaniments are the problems of lithography and material defects affecting the yield and quality of the chip beyond nanometer process. Via defects and congested wires are not beneficial for manufacturing in clock network and they should be avoided in the design. In this thesis, we refine these defects by layer assignment and formulate this assigning problem as conflict graph. The conflict graph is solved by maximum independent sets in each layer recursively and experimental results show almost 79.12% reduction rate of vias and 100% avoidance of all wires suffered in serious optical proximity effect in X architecture clock tree. In addition, we also evaluate the side effects and propose some strategies for the integration of design for manufacturability.

並列關鍵字

DFM ； non-Manhattan routing ； zero skew ； clock tree ； OPC ； redundant via ； X-architecture clock tree

參考文獻

[1] J.-T. Kong, “CAD for Nanometer Silicon Design Challenges and Success,” IEEE Trans. VLSI, vol. 12, pp. 1132-1147, Nov. 2004.

[2] S. Raghvendra and P. Hurat, “DFM: Linking Design and Manufacturing,” Proc. VLSID, pp. 705-708, Jan. 2005.

[3] A. Balasinski, “DfM for SoC (Design-for-Manufacturability for System on a Chip),” Proc. IDEAS, pp. 41-46, July 2005.

[4] D. Sylvester, “Design for Manufacturability: Challenges and Opportunities,” Proc. ASIC, pp. 1169-1171, Oct. 2005.

[5] J. Xuemei, Z. Peiyong, S. Zheng, and Y. Xiaolang, “Design for Manufacturability of Sub-100 Nanometer Standard Cells,” Proc. EDSSC, pp. 833-836, Dec. 2005.

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整合可製造性設計方法於X時脈樹

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