全數位元件組成之低壓降穩壓器與單電感三輸出直流直流降壓轉換器設計

Design of All Digital Components Low Dropout Regulator and Single-Inductor Triple-Output DC-DC Buck Converter

鄭筌鴻(Chuan-Hong Zheng)

指導教授 ： 陳建中 ； 黃育賢

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2009年)

摘要

本論文的第一個部份為全數位元件組成之低壓降穩壓器設計，提出數位控制迴路低壓降電壓調整器，利用數位電路對雜訊的敏感度低、對溫度和製程變異的影響度低、功率消耗較低…等優點，並降低電路功耗消耗，延長電池使用時間，而控制電路簡單也為電路一大優點，只使用八個反相器元件做控制。全數位元件組成之低壓降穩壓器電路使用台灣積體電路公司零點一八微米一層多晶矽六層金屬互補式金屬氧化物半導體製程來實現，晶片面積為0.314 x 0.561 mm2 (包含PADs)。
本論文第二部份為單電感三輸出直流直流降壓轉換器設計，製作兩顆晶片控制迴路分別使用電壓控制方式與電流控制方式。電路架構使用一個電感便能輸出三組直流電壓，減少電感的使用以節省整體電路面積與ＥＭＩ的問題。選擇充電路徑電路採用的控制機制是在比較三組輸出電壓值分別與參考電壓的差值來選擇充電路徑。第一顆晶片為電壓式脈波寬度調變技術，第二顆晶片為電流式磁滯電流技術，電路均使用台灣積體電路公司零點三五微米兩層多晶矽四層金屬互補式金屬氧化物半導體製程來實現，晶片面積分別為1.53 x 1.79 mm2 (含PADs)與 1.31 x 2.03 mm2 (含PADs)。

關鍵字

直流對直流轉換器 ； 低壓降穩壓器 ； 單電感多輸出 ； 降壓轉換器

並列摘要

The first part of this thesis is all about digital low dropout regulator, proposing a closed-loop digital control regulator to take some advantages of low sensitivity to noise, low sensitivity to temperature, low sensitivity to process variations, and low power consumption, etc…, to improve the power consumption efficiency and to extend battery life. The advantage of controller circuit is simple which only uses eight inverter controllers. The low dropout (LDO) circuit is implemented with 1.8-V TSMC 0.18μm CMOS 1P6M processes, and the chip area is 0.314 × 0.561 mm2 (with PADs).
The second part of this thesis introduces the design of Single-Inductor Tri-Output DC-DC buck converter. The author designed two different chips, one design uses voltage control closed-loop and the other uses current control closed-loop. The circuit design using an inductor can generate three different DC voltage levels and can reduce the chip size. The controller mechanism selects one recharging path at a time by comparing three output voltages with the corresponding reference voltages. The first chip is produced with the Pulse-Width-Modulation (PWM) technology and the chip area is 1.53 × 1.79mm2 (with PADs). The second chip is produced with the Hysteresis-Current-Controlled (HCC) technology and the chip area is 1.31 x 2.03 mm2 (with PADs).Which are implemented in 3.3-V TSMC 0.35μm CMOS 1P4M processes.

並列關鍵字

dc-dc converter ； low dropout regulator ； single-inductor multi-output ； buck converter

參考文獻

[5] 杜宜融，單電感雙輸出降壓轉換器與D類放大器設計，國立台北科技大學，電腦與通訊研究所，碩士論文，2008。

[26] 陳建豪，定頻式主動電流感測技術之磁滯電流控制直流-直流轉換器，國立台北科技大學，電腦與通訊研究所，碩士論文，2007。

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