- 學位論文
運算放大器之最佳化應用於管線式類比數位轉換器設計
Optimization of Op-Amp Applied to Pipelined A/D Converter Design
摘要
在本篇論文中我們以快速模擬退火演算法為核心，並且應用PERL語言來實現了一個運算放大器的電路尺寸設計自動化流程。此一自動化流程除了可以幫使用者調整電路內所有元件尺寸來達到目標規格外，其中也包含了我們所提出的運算放大器特殊測試電路，可用來節省耗費在電路模擬及規格量測的時間。 另外在每個階段的尺寸調整過程中，演算法也會進行動態調整，將每個變數的調整範圍做適度的收斂，如此程式便可以從更有效的解空間中，更快速的找到能符合目標規格的解。 此外演算法還可以從自動化的過程中，藉由記錄每個階段的模擬結果，來進一步推算更適合電路的目標規格，並且在自動化的過程中就做出動態調整，此功能對於尋找電路的效能極限有相當大的助益。 而同時我們也提出了一個電路搜索自動化的流程，此流程可以在電路有效能缺陷時，藉由讓原始電路產生型變的方式，幫助使用者進行電路架構的改良，使得效能缺陷可以得到改善。 另一方面，我們也將此自動化流程應用到管線式類比數位轉換器的設計上，我們僅需將電路的系統架構設定完成，就可以把電路交由自動化流程來設計尺寸；等待流程結束後，再把尺寸設計結果套用進系統中，如此就能完成一個管線式類比數位轉換器電路。最後，我們也成功的設計出一個雙重取樣架構規格為10位元，取樣頻率為100MHz的管線式類比數位轉換器，其模擬結果SNDR可達61.1dB，ENOB為9.85bit，DNL介於-0.188~+0.155 LSB之間，INL介於-0.363~+0.399 LSB之間。而整體設計時程大約可以縮短到1天之內。
並列摘要
In this thesis, we choose the Fast Simulated Annealing (Fast SA) algorithm to be the core, which utilize the PERL script to achieve a device sizing automation flow of operational amplifiers. The automation flow can help the user to tune the all of the devices size in the circuit to meet the target specifications. Furthermore, it includes a special testbench of operational amplifiers we proposed, which can be saved the time cost in circuit simulation and specification measurement. In the each stage of the size tuning flow, the algorithm will proceed a dynamic tuning step to converge the variable range moderately. So that search engine can find out the target specifications in the effective solution space quickly. Moreover, the algorithm can also record the results at each stage from the automation flow, and calculate the new target specifications which are more suitable for the circuit; and further, it could execute the dynamic tuning within the automation flow. Hence, this step is benefit to help us to find out the limit of the circuit performance. Furthermore, we proposed an automatic circuit exploration flow. This process can transform the original circuit to help users improving circuit performance when the circuit has some drawbacks. On the other side, we have utilized this process apply to a pipelined A/D converter design. We just need to set the system structure accomplish, and the sizes tuning could be completed by the circuit design automation flow. After the process finished, we place the results into the system, thus we could finish a pipelined analog-to-digital converter system design. Finally, we has successfully implemented a double-sampling architecture and specifications for 10-bit, 100MHz sampling rate of the pipelined analog-to-digital converter, the simulation results shows SNDR is up to 61.1dB, ENOB is 9.85 bits, DNL between -0.188 and +0.155 LSB, INL between -0.363 and +0.399 LSB. And the overall design time can be shortened to 1 day.