嵌入式多處理器FPGA系統之軟硬體分割技術

Hardware Software Partitioning for Embedded Multiprocessor FPGA Systems

鄭育旻(Yu-Min Cheng)

指導教授 ： 李宗演

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

https://doi.org/10.6841/NTUT.2006.00218

摘要

由於系統晶片快速的發展下，嵌入式系統也逐漸朝向多處理器的架構發展，而軟硬體共同設計是主要的設計方法，其中軟硬體分割為其重要的技術。本論文中提出使用GHO (Genetic with Hardware Oriented)軟硬體分割方法來達成在嵌入多處理器之FPGA (Field-Programmable Gate Array)系統下執行系統之軟硬體分割。此分割方法主要結合基因演算法(Genetic Algorithm)與硬體導向(Hardware Oriented)軟硬體分割方法，使得到的軟硬體分割解能在滿足系統規格限制下，有較短的系統執行時間、使用記憶體容量較少的優點。軟硬體分割之系統限制以系統執行時間(Execution Time)、費用(Cost)、功率消耗(Power Consumption)、處理器的個數為主。最後提出三個實驗來驗證本論文所提方法之有效性，分別是一個簡單的CDFG (Control and Data Flow Graph)例子、自適應差分脈衝編碼調製(Adaptive Pulse Code Modulation，ADPCM)系統、JPEG (Joint Photographic Experts Group)影像壓縮編碼系統。實驗結果得知，使用GHO軟硬體分割方法得到的軟硬體分割解具有系統執行時間較短、使用記憶體容量較少等優點。

關鍵字

嵌入式系統 ； 軟硬體分割 ； 基因演算法 ； FPGA系統 ； 影像處理

並列摘要

Multiprocessor architecture is nowadays gradually applying on embedded systems because the System-on-a-chip developed rapidly. Hardware software codesign is becoming a novel and practical solution for modern system design. The hardware software partitioning is an important step in the hardware software codesign. In this thesis, we propose a Genetic with Hardware Oriented (GHO) algorithm for hardware-software partitioning on multiprocessor embedded systems. The GHO algorithm combines Genetic algorithm (GA) and Hardware Oriented partitioning method to generate a system partitioning solution which has high performance and low memory size under satisfaction with system constraints. The system constraints for hardware-software partitioning include system execution time, cost, power consumption and number of processor. Finally, three design examples, namely a simple CDFG (Control and Data Flow Graph), Adaptive Pulse Code Modulation (ADPCM) system and Joint Photographic Experts Group (JPEG) encoding system, are used to illustrate the feasibility of our proposed GHO partitioning method. Experiment results show our purposed GHO algorithm can obtain a solution which has shortering system execution time and lesser memory used size.

並列關鍵字

Embedded Systems ； Hardware Software Partitioning ； Genetic Algorithm ； FPGA System ； Image Processing

參考文獻

[2]W. Wolf, “A Decade of Hardware/Software Codesign,” IEEE Computer, Vol. 36, pp. 38-43, 2003.

[3]R. Ernst, “Codesign of Embedded Systems: Status and Trends,” IEEE Design and Test of Computers, Vol. 15, No. 2, pp. 45-54, April-June 1998.

[4]N. S. Woo, A. E. Dunlop and W. Wolf, “Codesign from Cospecification,” IEEE Computer, Vol. 27, pp. 42-47, 1994.

[5]R. K. Gupta, N. C. Claudionor and G. De Micheli, “Program Implementation Schemes for Hardware-Software Systems,” IEEE Computer, Vol. 27, No. 1. pp. 48-55, Jan. 1994.

[6]C. J. N. C. Jr, D. C. D. S. Jr and A. O. Fernandes, “Hardware-Software Codesign of Embedded Systems,” Proceedings of the XI Brazilian Symposium on Integrated Circuit Design, pp. 2-8, 1998.