65 nm世代pMOSFETs的有效邊緣寬度及其在升溫熱載子加壓下之變化

Effective Edge Width for 65 nm pMOSFETs and Their Variations under HC Stress at Elevated Temperature

廖青松(Ching-Sung Liao)

指導教授 ： 陳雙源 ； 黃恆盛

國立臺北科技大學/機電學院/機電整合研究所/碩士(2009年)

https://doi.org/10.6841/NTUT.2009.00368

摘要

就矽基半導體而言，由於電洞的平均自由徑較電子短，且遷移率也較電子差，在室溫約為電子的三分之一，所以在過去的研究中，皆認為nMOSFETs因熱載子所造成的特性劣化，遠比pMOSFETs嚴重。然而在電晶體進入深次微米及奈米尺度後，上述情況似乎已改變，而pMOSFETs的熱載子可靠度也成為一項新的問題。另外，現今CMOS技術中，淺溝槽絕緣(STI)不可避免地使用於電晶體之間，但其對於熱載子(hot-carrier)可靠度的影響，至今仍未確定，特別是窄寬度的pMOSFETs。
在本研究中，採用聯電65 nm製程，通道長度為0.06 μm，閘極氧化層為19.5 Å，寬度分別為10 μm、1 μm與0.12 μm之pMOSFETs作為實驗樣本，來進行通道熱載子（CHC）與汲極雪崩熱載子（DAHC）加壓測試，而測試的溫度分別是25℃、85℃與125℃三種。加壓實驗前後皆對電晶體量測I-V等特性，藉其物理特性、熱載子與窄寬度(narrow-width)效應，來了解電流衰退的情形，並計算有效邊緣寬度 (△w)，對元件電性劣化的影響與了解其在升溫熱載子加壓下之變化。結果發現，與寬通道元件比較，窄通道pMOSFET之臨界電壓與汲極電流退化較嚴重，是因為STI邊緣區域的熱載子注入率較高，而使其電晶體性能加速退化。CHC也較DAHC嚴重，CHC加壓測試後，介面狀態和氧化層陷入電荷主要在STI邊緣與通到中心區域產生，而造成嚴重地臨界電壓漂移與汲極電流劣化。從實驗結果發現，△w是在臨界電壓與汲極電流劣化中佔主要因素，因此，窄通道元件比寬通道元件更加劣化。

關鍵字

熱載子 ； 淺溝槽絕緣邊緣 ； 可靠度 ； 窄寬度 ； 溫度 ； 有效邊緣寬度

並列摘要

On the basis of the semiconductor of silicon, the mean free path of holes is shorter than electrons, and hole’s mobility is slower than electrons about one third of the electrons at the room temperature. Therefore, the hot-carrier inducing characteristic degradation in nMOSFETs was considered much more severely than that in pMOSFETs. However, as the transistor channel length has been scaled down into deep submicron and nano scale, the previous concepts may not valid again and the hot-carrier reliability of pMOSFETs has gradually become a significant issue. In addition, shallow trench isolation (STI) is inevitable to be used in isolating the between transistors in today COMS technology on the narrow width pMOSFETs.
In the work, pMOSFETs on wafers from 65nm node of UMC were characterized. The pMOSFETs used in this experiments have W=10 μm, 1 μm and 0.12 μm with 19.5 Å gate oxide thickness, all the Lg=0.06 μm. The devices were stressed under channel hot-carrier (CHC) and drain avalanche hot-carrier (DAHC) condition at temperatures of 25, 85 and 125 ℃. After experiments, I-V measurements were used to characterize the physical properties, hot-carrier effect and narrow-width effect. It can understand from current degradation, and calculated the effective edge width (△w), that is discussed on affected electrical characteristics degradation, and realized their variations under HC stress at elevated temperature. Comparing with the wide width pMOSFET, the experimental results discovered that the narrow width pMOSFET have more degradation of threshold voltage and drain current. It is believe that the transistor characteristic accelerate degradation due to have higher the hot-carrier injection (HCI) rate at STI edges region. CHC stress results more serious degradation than DAHC too. It consider that CHC stress produce interface states and oxide trapped charges both on STI edges and channel center region, causing threshold voltage shifts and drain current degradation seriously. From the experimental result, the degradation in threshold voltage and drain current are dominated by △w, and hence the narrow width device presented the worse degradation than wide width one.

並列關鍵字

Hot Carrier ； shallow trench isolation edge ； Reliability ； Narrow Width ； Temperature ； effective edge width

參考文獻

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