應用於高解析度影像系統處理之高可靠度FPGA實作

隨著科技不斷的進步，目前影像品質已經進入Full HD (Full high-definition, 全-高畫質)的時代。其解析度是超過1920x1080像素且其畫面更新率需達60 fps (frames per second)。因此，本研究以FPGA為基礎，我們實作一個高可靠度影像處理系統平台來處理Full HD影像。我們應用一套高可靠度的硬體平台開發流程，藉由模擬軟體的輔助下，能事先模擬出高速數位信號在PCB上的信號傳輸的完整性。所模擬的佈局規範提供製作硬體時作設計使用，其可靠度達約90 %以上。因此，本研究方法可以降低製作PCB的次數，進而降低硬體製作成本。應用本研究策略來實作實作一個以FPGA為基礎的高可靠度的影像處理系統平台。在本系統中，我們以DDR2之Clock與DQS訊號線長度控制在於555 mil為主要討論目標。tDQSCK模擬值為195.048 ps和其實際量測值215 ps；根據JEDEC規範其值必需小於350 ps。模擬與實際量測誤差率約是9.3 %，符合可靠度達之要求。我們的佈局訊號線長度比JEDEC規範有38.5 %的較佳效能。我們評估Full HD影像輸入端與輸出端的眼圖效能。在LVDS輸入訊號下，眼圖寬度及高度的標準值分別為1.092 ns與100 mV，我們實際量測為1.297 ns與149 mV。因此，我們的效能是比標準值分別好18 %與49 %。在HDMI輸出訊號下，眼圖標準值約是424 ps與400 mV，實際量測結果約為540 ps與600 mV。更進一步，我們的效能是比標準值好約27 %與50 %。從以上量測結果，證明我們的Full HD影像系統處理平台設計是高可靠度。

關鍵字

高解析度；影像系統處理； CCD ； FPGA ；高可靠度；頻寬

並列摘要

With the progress of the science and technology, the image quality has reached an era of the Full HD (Full high definition). Its resolution is over 1920x1080 pixels and the refresh rate is over 60 frames per second (fps). Therefore, we implement a Full HD image system processing platform for processing the Full HD image based on FPGA in this study. We employ the development process of the high-reliability hardware platform, whose process can simulate the signal integrity of the high-speed digital signal on the PCB transmission before the hardware implementation by the software simulation tool. The simulated layout rulers can be used in the hardware implementation, and its reliability can be over 90%. Therefore, our approach can reduce to produce the number of the PCB times, and then it can reduce the hardware implementation cost. Apply our methodology to implement the high-reliability image system processing platform based on FPGA. The signal length of clock and DQS of DDR2 are under controlled as 555 mil as the major discussion objective in our system. The simulation result (real measurement respectively) of tDQSCK is 195.048 ps (215 ps respectively), and its value must be less than 350 ps according to JEDEC ruler. The error rate between the simulation and real measurement is about 9.3% to meet the requirement of the high-reliability. The length of our layout performance is about 38.5% better than that of the JEDEC rulers. We evaluate the eye diagram of the Full HD input and output. Under the LVDS input signal, the standard eye width and height are 1.092 ns and 100 mV, respectively, and our real measurements are 1.297 ns and 149 mV, respectively. Hence, our performances are about 18% and 49%, respectively, better than the standard. Under the HDMI output signal, the standard eye width and height are 424 ns and 400 mV, respectively, and our real measurements are 540 ns and 600 mV, respectively. Moreover, our performances are about 27% and 50%, respectively, better than the standard. From the above measurement results, we know that the design of our Full HD image system processing platform is high-reliability.

並列關鍵字

High-Resolution ； Image System Process ； CCD ； FPGA ； High-reliability ； Band-width.

參考文獻

[4] High-Definition Multimedia Interface Specification Version 1.4b October 11, 2011.

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應用於高解析度影像系統處理之高可靠度FPGA實作

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