以SOPC實現諧波型EDFT之相量計算

SOPC-based Harmonic EDFT Phasor Calculation

周書宇(Shu-Yu Chou)

指導教授 ： 蔡孟伸

國立臺北科技大學/機電學院/自動化科技研究所/碩士(2010年)

摘要

相量計算的實現方式有許多種，其中以離散傅立葉轉換(Discrete Fourier Transform, DFT)最常被為使用。由於類比數位轉換器(Analog to Digital converter, ADC)取樣時間無法與待測訊號同步，可能會產生頻率偏移之現象，使得離散傅立葉轉換在計算時會產生洩漏效應(Leakage Effect)，造成相量計算的不準確。而經由DFT所發展出來的Extended Discrete Time Fourier Transform(EDFT) family，其中基本型EDFT能有效修正頻率偏移之現象，但對於諧波的干擾仍會產生誤差。所以本文採用諧波型之EDFT演算法，不但保有DFT原有之優點，也可解決頻率偏移與諧波干擾的影響。
本研究以SOPC(System on a Programmable Chip)來實現整個系統的架構，主要可分為硬體與軟體兩部分。前半部係透過硬體平行運算的特性實現DFT，並結合查表法使得DFT運算速度提升；後半部則將DFT運算結果傳送至NIOS II軟體端上作演算法的處理，即可獲得正確之信號頻率、振幅與相位。未來若需更改演算法，只需透過軟體的修改即可完成。本文系統硬體架構採用VHDL(Very High Speed Integrated Circuit Hardware Description Language, VHDL)建置模組，並使用Modelsim模擬器進行模擬以確認硬體設計的正確性，最後再將完整的設計合成於FPGA上。開發完成的系統透過訊號產生器來進行最後結果的驗證。

關鍵字

DFT ； EDFT(延伸型離散傅立葉轉換) ； 相量計算 ； FPGA

並列摘要

Discrete Fourier Transform (DFT) is the mostly implemental method for phasor calculation. When frequency shifts, the leakage effect from DFT will occur during the phasor calculation. Because of the leakage effect, the calculated phasor values are not very accurate. In order to overcome this problem, basic Extended Discrete Fourier Transform (EDFT for short) can be used to diminishing the frequency shift phenomenon. Unfortunately, the harmonic components can also influence the results of computed phasor values.The basic EDFT cannot resolve this problem. The EDFT family that includes EDFT, harmonic EDFT and so on is extended from the basic DFT. By using the harmonic EDFT, the advantages of DFT can be maintained while, the above-mentioned problems can also be solved.
In this thesis, the harmonic EDFT is implemented using SOPC (System on a Programmable Chip) development system. The development system contains software and hardware. The VHDL module is verified by utilizing Modelsim simulator. The parallel computing property and looking-up method are implemented in the proposed system, the computation speed for DFT is improved quite substantially. The computed results from DFT are acquired by the NIOS II, a 32-bit RISC based microprocessor. When the phasor computation is completed, the signal information (i.e., amplitude, frequency, and phase angle) can be obtained. In order to verify and validate the performance of the developed system, controlled signals generated from a function generator is applied.
For the future extension, the hardware can be remained untouched while the software algorithm is modified for advanced applications.

並列關鍵字

DFT(Discrete Fourier Transform) ； EDFT(Extended Discrete Fourier Transform) ； Phasor Calculation ； FPGA

參考文獻

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