新型適應性疊代演算法之渦輪碼解碼器晶片設計

IC Design of Turbo Decoder Using New Adaptive Iteration Algorithm

詹昆達(Kun-Ta Zhan)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

本論文提出一個以低功率為訴求之渦輪碼解碼器之超大型積體電路架構設計。我們主要提出三個方法來改良渦輪碼解碼器之功率消耗，一為新型提早終止疊代演算法，利用附帶資訊彼此間的關係做為一個終止策略，用以終止多餘不必要的疊代計算，節省計算時所消耗的功率；二為混合式記憶體的軟式輸入軟式輸出解碼器架構，用以降低軟式輸入軟式輸出解碼器內儲存狀態記憶體空間來節省功率消耗；最後提出臨界最大值正規化電路架構，在不影響解碼效能的情況下，減少狀態計量值的運算次數，藉此降低功率消耗。
最後，我們將所提之新型適應性疊代之渦輪碼解碼器先以Xilinx Vertix-4的FPGA來進行驗證再以cell-based流程完成晶片設計。實驗證明，在新型適應性疊代的記憶體使用量我們節省了9.3%~15.5%的記憶體面積以及2.2%~12％的位元使量，而在軟式輸出軟式輸入解碼器架構上比起傳統的架構約可省下23%~40%的記憶體面積以及42%~54%的位元使量；另外就新型正規化電路中，相較於典型最大值正規化電路，也可節省43.8%~89.4%的功率。最後我們也實際以TSMC .18um 1P6M製程，完成一顆新型適應性疊代演法之渦輪碼解碼器晶片設計，當系統工作在97.5MHz的頻率下時，其產能為7.9~23.6M bits/sec，整個電路含IO PAD的面積為2.14x2.14mm2。

關鍵字

渦輪碼解碼器 ； 低功率 ； 適應性疊代演算法

並列摘要

In this thesis, we propose a new VLSI architecture for low-power turbo decoder. This architecture includes three parts to improve power dissipation properties. Firstly, we propose a new adaptive iteration algorithm that can employ extrinsic information character to avoid unnecessary iterations. Secondly, we develop a hybrid architecture for the SISO decoder which decreases the state storage space and power consumption. Finally, we propose a new normalization technique which can reduce the state metric calculation without decoding performance loss. We also use Xilinx Vertix-4 FPGA to verify this new adaptive turbo decoder. Experiments show that we gets 2.2~12.2％ memory bits size and 9.3~15.5％ memory area saving in comparison with other stopping iteration algorithms. In our SISO decoder, we can save 42~54% memory bits size and 23~40％ memory area. In state metric normalization, we can save 43.8~89.4％ power consumption in our architecture. Finally, we have designed this new adaptive turbo decoder by TSMC .18μm 1P6M process. When operation frequency is 97.5MHz, the throughput of this decoder is 7.88~23.64Mbps, and chip size including I/O PAD is 2.14x2.14mm2 .

並列關鍵字

Turbo decoders ； Low-power ； Adaptive iteration algorithm

參考文獻

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