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  • 學位論文

Google Android系統平台上能耗導向之動態電壓頻率調整演算法之設計與實作

Design and Implementation of an Energy-aware DVFS Algorithm for the Google Android Operating System

指導教授 : 梁文耀

摘要


由於科技的進步,手持式裝置等熱烈發展,使得行動商務越來越受到期待。生活中也隨處可見嵌入式系統之相關應用。而目前可攜式行動裝置大都以電池做為主要供電來源,如何做電源有效的管理,延長電池的生命週期則是一門值得研究之重要議題。 本研究以Creator PXA270開發板為實驗平台,開發以能耗導向之動態電壓頻率調整演算法。利用處理器所提供的效能監控單元(Performance Monitor Unit, PMU)觀察系統執行狀態,取得系統記憶體存取比例(Memory Access Rate, MAR)。藉由執行多種測試程式(benchmark),分析出不同的記憶體存取比例下分別對應的最低能耗頻率(Critical Speed),確保系統以最低的能耗完成所需要之工作。 我們已分別實作出Linux核心(Linux Kernel)、使用者空間(User Space)以及Android系統服務(Android Service)三種動態頻率調整策略,並且在降低能量消耗有顯著的效果。

並列摘要


In recent years, handheld devices become more and more popular, and it is highly integrated into people’s daily live. Because almost all the embedded devices only use the batteries as major power source, it becomes an important issue for controlling power consumption and extending the battery lifetime. In this paper, we choose the Creator PXA270 development broad as our experiment target. Intel PXA270 processor provides performance monitor units (PMU) for developers to monitor the status of processor. By execute several benchmarks of MiBench and monitor the PMU of running benchmarks, we discover that each benchmark has its own feature, and we define a memory access rate (MAR) to represent the feature of program which can calculate by PMU. We also observe that lowest energy consumption usually appears at some CPU frequency other than the lowest frequencies, and this frequency is defined as the critical speed. According to the relationship between MAR and critical speeds, we construct a correlation equation called MAR-CSE that can predict the critical speed by giving a MAR value at runtime. We also have implemented three DVFS governors in kernel space, user space and Android Service base on MAR-CSE. The results show that the energy consumption can be effectively reduced.

並列關鍵字

Low Power Energy Consumption Embedded DVFS Android JNI Power Management Intel PXA270

參考文獻


[2] N. K. Jha, "Low-power system scheduling, synthesis and displays," Computers and Digital Techniques, IEE Proceedings -, vol. 152, pp. 344-352, 2005.
[6] L. Benini, A. Bogliolo, and G. De Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 299-316, 2000.
[9] R. Jejurikar and R. Gupta, "Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems," in Proceedings of the 2004 international symposium on Low power electronics and design, 2004, pp. 78-81.
[10] R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 275-280.
[11] J. Choi and H. Cha, "Memory-aware dynamic voltage scaling for multimedia applications," IEE Proceedings - Computers and Digital Techniques, vol. 153, pp. 130-136, 2006.

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