- 學位論文
高壓LDMOS元件製程設計與相關特性分析
High Voltage LDMOS Device Process Design and Related Properties Analysis
摘要
通常，高壓橫向雙擴散金氧半場效體(LDMOS)結構係被操作在20~700 伏高壓範圍。由於易與單晶片整合，且能同時在CMOS 或BiCMOS 製程中被製造，而被廣泛採用。 本論文乃借助Tsuprem-4 和Medici 模擬軟體詳細討論分析了高壓N-LDMOS 元件的基底濃度、漂移區濃度、長度、源極區、摻雜參數與崩潰電壓之間的關係，透過對各參數的模擬與元件設計，最終得到兼具抗靜電能力的高壓N-LDMOS 最佳結構、製程參數。 透過I-V 特性曲線與 ESD 測試結果顯示此高壓N-LDMOS 元件的崩潰電壓可達到500V 以上且抗靜電能力，HBM 能承受超過2.5KV，MM 能承受超過200V 的業界標準.並且製程簡單，元件所佔面積不大，可以廣泛地應用於各種高壓用途上。
並列摘要
In general the high voltage laterally double-diffused metal oxide semiconductor (LDMOS) structure is operated in the high voltage range 20~700V. Since it can easily be integrated on a single chip and manufactured in CMOS or BiCMOS process and be widely applied. In this thesis the relations of the breakdown voltage to the substrate concentration the drift dose energy and length and the doping conditions of source area have been discussed in detail with the two soft wards : Tsuprem-4 and Medici. The optimal high voltage N-LDMOS was proposed after the simulation on the parameters of the N-LDMOS. The breakdown voltages of the given N-LDMOS exceed 500 V both in the off-and on-state which can be seen from the I-V Characteristic curves. The presented N-LDMOS can be well applied in the high voltage power ICs for its simple process. ESD Protection level in excess of 2.5KV with human body model (HBM) and 200V with machine model (MM) have been shown to be feasible for this device.