- 學位論文
使用適應性滑動視窗演算法之低功率渦輪解碼器晶片設計
Chip Design for Low Power Turbo Decoder using Adaptive Sliding Window Algorithm
摘要
渦輪解碼器以其解碼產生的額外資訊，循環利用於疊代解碼，使其錯誤更正能力接近於仙農極限。本論文提出一種新型適應性視窗之渦輪解碼法，該一方法主要是偵測解碼器內部已收斂的視窗，並在疊代次數依然相同的情況下，藉由停止渦輪解碼器內部已收斂視窗的解碼程序，來達到低功率且高效能的訴求，之後，我們更進一步的提出可提高渦輪解碼吞吐量的適應性視窗渦輪解碼器架構，不只節省功率，更可縮短解碼平均的時間，來達到現今無線通訊系統高傳輸量的需求。 經由模擬數據及實體電路設計證明，所提出的適應性視窗解碼硬體只需增加整個渦輪解碼器4.7％的硬體，即可在訊雜比2.5dB、臨界值6時，相對於傳統八次疊代的渦輪解碼器，平均可以節省62.92％的後向計量值以及對數概似機率的計算次數，而加速解碼時，解碼平均時間只需傳統的42.63%即可。最後我們將我們所提出的適應性視窗渦輪解碼器先以Xilinx Veritx-4 FPGA進行驗證，再以TSMC 0.18um 1P6M製程，完成一顆適應性視窗演算法之渦輪碼解碼器晶片，驗證當系統工作在77MHz的頻率下時，其產能為4.3~13.76 Mb/s，而整個晶片含IO PAD的面積為 1.91x2.17平方公釐。
並列摘要
Turbo code was proposed by exchanging its extrinsic information between two phase iteratively, and well know as its high performance that near Shannon limit. In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Further more, we proposed a VLSI architecture that also increases the throughput of Turbo decoder. Experimental results show that the new adaptive sliding window method only slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times of the Turbo decoder. When we set threshold to 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be skip or stop, 57.37% decoding time can be save in comparison with traditional Turbo decoder doing eight times of iterations. Finally, we have verified this architecture using Xilinx Vertix-4 evaluation board ML-402, and designed the decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3~13.76 Mb/s, and whole chip size including IO PAD is 1.91x2.17mm^2.