- 學位論文
虛擬快閃型電流模式類比數位轉換器之設計與實現
Design and Implementation of a Pseudo-Flash Current-Mode Analog to Digital Converter
摘要
目前的類比數位轉換器因處理訊號的取樣技巧不同，有許多不同的架構存在，低解析度(low resolution)的快閃型類比數位轉換器(FLASH ADC)屬於平行式來處理輸入訊號，故具有較佳的訊號轉換速率；於是又有串列式架構與較高解析度(6-bit以上)的管線式類比數位轉換器 (Pipe-lined ADC)，大大降低運算放大器使用數量與功率消耗，適合運用在中速度的訊號處理；另外還有利用訊號調變技巧的三角積分調變器(Sigma-Delta Modulator)來達到高解析度、低速度的應用領域，其中使用了超取樣(over-sampling)與雜訊移頻(noise shaping)兩大技巧。 本文中提出了另一種新型串列式架構，稱為虛擬快閃型(Pseudo-Flash的)電流模式類比數位轉換器，利用電流傳輸器(current conveyor)的極佳電流追蹤特性來針對輸入電流訊號作取樣動作；其中所用的主要電路如：電流鏡、電流放大器、取樣保持電路皆以電流傳輸器所組成；其電路架構與訊號取樣方式類似管線式類比數位轉換器，但卻與管線式完全不相同的取樣技巧，並且類似FLASH ADC具有一個時脈週期即可完成訊號取樣能力。 整個電路共串接了七個取樣級(1-bit/stage)與一組參考電流源(reference current source)，其中每一個取樣級包含了三個電流傳輸器與一個電流比較器，整個電路使用台積電TSMC CMOS 0.35μm mixed-signal 2P4M polycide製程技術，取樣頻率為12.5MHz，輸入訊號動態範圍0~400μA；在直流準確度上，微分非線性度+0.22∼-0.38 LSB，積分非線性度+0.5∼-0.08 LSB，總功率消耗為112.3mW，整個晶片尺寸(包含I/O Pads)總共為1.208 x 1.351 mm2。
並列摘要
There are many different structures existed due to analog to digital converter using different sampling methods. The Flash Analog to Digital Converter (FLASH ADC) is the parallel structure used for low resolution which can provide better sampling performance. Using series of structure of Pipe-Lined ADC would increase higher resolution (more than 6-bits) and reduce the number of comparator and power consumption which was suitable for medium speed application. Sigma-delta modulator (SDM) became another modulation method to provide the high resolution for low speed application. In using was over-sampling and noise shaping techniques. This paper proposed a new structure of “Pseudo-Flash Current-Mode Analog to Digital Converter” which used well current tracking of current conveyer. The major circuit is altered from current conveyer such as current-mirror, current amplifier, current-mode sample-and-hold circuit. The new structure is same as pipe-lined ADC, but it is not alike all. The Pseudo-Flash like FLASH ADC can get all data in one clock cycle. All of the circuit has connected seven sample-stages and one reference current source. Each 1-bit/stage has included three current conveyers and one comparator. The whole circuit implemented with process of TSMC CMOS 0.35μm mixed-signal 2P4M polycide. The sampling rate is 12.5MHz, DNL is -0.38~+0.22LSB, INL is -0.08~+0.5LSB, respectively total power consumption and die size are 112.3mW and 1.208x1.351mm2.