本論文藉由基因演算法重新尋找多模組記憶匯流排傳輸路徑上之傳輸線阻抗值。考慮傳輸線為無損,並利用反射及傳輸係數之公式,可定義出適應函數。也就是令多模組記憶匯流排之反射係數為0、傳輸係數為1,如此便能使接收端達到最大功率。 資料訊號具有讀與寫的雙向特性,需定義從中央處理器傳至雙列直插式記憶體模組0和雙列直插式記憶體模組1以及雙列直插式記憶體模組0傳回中央處理器和雙列直插式記憶體模組1傳回中央處理器等四組適應函數。藉由基因演算法之適應函數的特性可輕易的將各狀態之適應函數合併為一個適應函數,即各個狀態之適應函數相加。從眼圖結果可看出不論是讀或寫之狀態的訊號完整性皆相近。基於這樣的特性,本研究也可輕易地拓展到解決多根雙列直插式記憶體模組因阻抗不匹配所造成的訊號失真的問題。
The purpose of this experiment was to optimize the multi-module memory bus by using genetic algorithm. In this paper, the experiment results on lossless transmission line were presented to define fitness function by using the formula of reflection and transmission coefficient; that is, reflection coefficient equal to zero and transmission coefficient equal to one. Therefore, the receiver can make the largest power. This study explored the transmission of data signal working on write and read state. The fitness function is composed of four fitness functions – from CPU to Dual In-line Memory Module 0(DIMM0), from CPU to DIMM1, from DIMM0 to CPU, and from DIMM1 to CPU. The four fitness function can be combined to form one new fitness function. The eye diagram showed that the signal integrity of write and read states were the same. Because of the advantage of characteristic, this study can solve the impedance mismatching problem in many DIMMs.