新型低功率、低延遲渦輪解碼器晶片設計

A New VLSI Architecture for Low-power and Low-Latency Turbo Decoder

蔡宗憲(Tzung-Shian Tsai)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

本論文提出以低延遲、低功率為訴求之渦輪碼解碼器之超大型積體電路架構設計。我們主要提出兩個方法來改良渦輪碼解碼器之功率消耗，第一藉由調整編碼端順序並設計一新型軟輸入軟輸出(SISO)滑動視窗流程，用以降低SISO解碼延遲及減少內儲存狀態記憶體空間；第二為採用ㄧ新式免運算動態後向狀態計量值，它有效改善SISO內部記憶體的擾動，也減少邏輯運算單元使用量，此外這兩種架構皆可將解碼延遲降到只剩1L，並且較傳統方法具更快速及更省功率。
在驗證上我們將所提之低功率渦輪碼解碼器先以Xilinx之Virtex4 FPGA來進行功率和面積的模擬及功能驗證，實驗結果，我們設計新型渦輪碼使用比起傳統的架構約可省下22.2 %的運算邏輯，功率消耗大大節省56.2%，在記憶體面積評估我們採用0.18um TSMC/Artisan Design Kit Memory製程來進行實體比較，有關渦輪碼之SISO輸出我們比起傳統節省約39.6%~61%。最後，使用TSMC 0.18μm 1p6m製程實際完成ㄧ顆新型低延遲低功率之免運算動態後向狀態渦輪解碼器晶片，晶片最高工作頻率為111.7MHz，面積大小2.1×2.1mm2。

關鍵字

渦輪碼解碼器 ； 低延遲 ； 低功率 ； 省記憶體

並列摘要

In this thesis, we propose a new VLSI architecture for low-power and low-latency turbo decoder. This architecture includes two parts to improve power dissipation properties. Firstly, we change turbo encoder data sequence and develop a new architecture for the soft-in-soft-out decoder which decreases the state storage memory space and power consumption. Secondly, we propose a new dummy-beta-free turbo decoder that can reduce calculation times and decreased memory access. Furthermore, the two architectures can achieve only 1L delay latency and have low power consumption.
For demonstrating this architecture, we have verified this novel low-power turbo decoder by Xilinx FPGA XLXHW-V4-ML420 system. The experimental results show that our architecture can reduce 39.6%~61% memory areas, decrease 56.2% power consumption and save 22.2% logic gate count in comparison with traditional decoder. Finally, we have designed a novel low-power turbo decoder with TSMC 0.18μm 1P6M technology. The maximum frequency of this decoder is 111.7MHz and chip size including I/O pad is 2.1×2.1mm2.

並列關鍵字

Turbo decoders ； Low-power ； Low-latency ； Memory saving

參考文獻

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