以可規劃邏輯陣列研製單級返馳式功因校正轉換器

Design and Implementation of FPGA-Based Single-Stage Flyback Converter

江顯元(Xian-Yuan Chiang)

指導教授 ： 賴炎生

國立臺北科技大學/電資學院/電力電子產業研發碩士專班/碩士(2008年)

https://doi.org/10.6841/NTUT.2008.00633

摘要

本文以可規劃邏輯陣列作為控制器，研製一單級返馳式轉換器，以元件位移及開關同步切換技術將傳統之雙級功因校正返馳式轉換器改為單級式功因校正返馳式轉換器。
利用可規劃邏輯陣列研製單級返馳式功因校正轉換器，可減少相關功率元件，使轉換器易於實現低瓦數應用。控制器使用可規劃邏輯陣列提供了模組化及數位化控制，其設計規格為:
輸入電壓 = 110 V/VAC，60 Hz
輸出電壓 = 12 V
額定輸出功率 = 40 W
為了達到數位控制器設計，本文推導此架構的小訊號數學模型，由模擬驗證，且使用可規劃邏輯陣列實現。實驗結果證實此轉換器之功率因數可達95%以上。

關鍵字

功因校正 ； 馳式轉換器

並列摘要

The objective of this thesis is to design and implement an FPGA-based single-stage flyback converter with power factor correction. Based upon the well known component placement and synchronous switching methods, the single-stage flyback converter with PFC is derived from its two-stage counterpart.
The advantages of the designed and implemented single stage flyback converter with PFC include reduction of power devices and the related driver. This kind of converter becomes very promising for low power applications. The controller is realized using FPGA to provide programmable capability and digital control. The design specifications are: input voltage = 110 V/AC, 60 Hz, output voltage = 12 V/DC and the rated output power = 40 W.
The small-signal model is derived for digital controller design. The derived model is confirmed by simulation and realized by FPGA. Experimental results show that the output voltage can be well regulated while keeping the input power factor greater than 95%. These results confirm the design and implementation.

並列關鍵字

Power Factor Correction ； Flyback converter

參考文獻

[25] 蕭賀璞，“新型半橋式單級電力轉換器之研製”，國立台北科技大學電機工程系電力電子產業研發碩士學位論文，民國96年七月。

[26] 賴建宏，“具有功因修正之單級順向式轉換器的研製”，國立台北科技大學電機工程系電力電子產業研發碩士學位論文，民國96年一月。

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