多維圖樣變動長度之測試資料壓縮法

由於超大型體電路技術的進步迅速，晶片的密度越來越高，使的晶片測試的難度也隨之上升，如龐大的測試資料、過長的測試時間、高功率的消耗和ATE (Automatic Test Equipment)的頻寬限制，皆造成測試成本的增加。為了要節省測試資料和測試時間，壓縮測試資料是一個常見且有效率的方法。本篇論文將利用run length code來表示test pattern的編碼資訊，來達成測試資料的壓縮。並採用多維空間的想法，來表達code的資訊。我們還會利用幾個方法來幫助壓縮，而這只需要幾個參數調整。而解壓縮非常簡單，不需要複雜的硬體架構。實驗結果將會說明此技術能提供高的壓縮率，來減少測試時間。

關鍵字

測試資料壓縮；多維圖樣變動長度；測試資料編碼；系統單晶片；自動測試機

並列摘要

The density of integrated circuits increases as the result of the VLSI technology grows up. Hence, testing for integrated circuit is more and more complex. Such as the huge growth of the test time, high power consumption and bandwidth restriction of ATE (automatic test equipment) are lead to the increase in cost of testing. The proposed method presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS’89 benchmarks.

並列關鍵字

test data compression ； pattern run-length ； code-based ； SOC ； ATE

參考文獻

[1] S. Mitra and K. S. Kim, “X-Compact: an efficient response compaction technique,” IEEE Trans. CAD, vol. 23, pp. 421-432, Mar 2004.

[3] S. Mitra and K. S. Kim, “X-Compact: An efficient response compaction technique,” IEEE Trans. CAD, vol. 23, pp. 421-432, Mar 2004.

[4] B. Koenemann, C. Banhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A SmartBIST variant with guaranteed encoding,” in Proc. Asia Test Symposium, 2001, pp. 325-330.

[5] N.A. Touba, “Survey of Test Vector Compression Techniques,” IEEE Des. Test Comput, vol. 23, no. 4, pp. 294-303, April 2006.

[6] D. A. Huffman, “A Method for the construction of minimum redundancy codes,” in Proc. IRE, vol. 40, 1952, pp. 1098-1101.

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多維圖樣變動長度之測試資料壓縮法

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